Local Interface RF Passivation Layer Based on Helium Ion-Implantation in High-Resistivity Silicon Substrates

Perrosé, Martin [CEA-leti] Acosta Alba, Pablo [CEA-leti] Reboh, Shay [CEA-leti] Lugo, Jose [CEA-leti] Plantier, Christophe [CEA-leti] Cardinael, Pieter [UCL] Rack, Martin [UCL] Allibert, Frédéric [SOITEC] Milesi, Frédéric [CEA-leti] Garros, Xavier [CEA-leti] Raskin, Jean-Pierre [UCL] et al.[show all]

An original method to locally fabricate interface passivation layers embedded in Silicon-on-Insulator substrates is presented. This method consists in creating defects under the Buried Oxide (BOX) thanks to helium implantation followed by thermal annealing. The performances of the resulting substrates were evaluated through RF characterizations using coplanar waveguide structures to extract effective resistivity and harmonic distortion. Both figures of merit (FoM) are greatly improved by the formation of buried defects layer, reaching 2 nd harmonics below −100 dBm and effective resistivities of 4 kΩ.cm. This performance is comparable to commonly used polycrystalline silicon Trap-Rich (TR) layers when measured with similar experimental conditions. Furthermore, we obtained RF performances that were stable with the bias voltage (between −15 V and + 15 V) and the operating temperature up to 100°C. This approach can efficiently be locally implemented on a wafer to create passivation layer, making it very promising in order to enable co-integration with Fully Depleted-SOI technology requiring back-gate access.