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Ultra-low power flip-flops for MTCMOS circuits

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Levacq, D. Dessard, V. Flandre, Denis [UCL]

This paper deals with new MTCMOS flip-flop architectures with high speed performance in active mode and ultra-low power dissipation in sleep mode. The use of new ultra-low leakage latch structure allows us to memorize the flip-flop state even during sleep mode and to strongly reduce the leakage in comparison with previous solutions.

Document type Communication à un colloque (Conference Paper) – Présentation orale avec comité de sélection
Publication date 2005
Conference "IEEE International Symposium on Circuits and Systems (ISCAS)", Kobe, Japan (23-26 May 2005)
Peer reviewed yes
Host document "proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS) (IEEE Cat.No. 05CH37618)"- Vol. 5, p. 4681-4 (ISBN : 0-7803-8834-8)
Publisher IEEE
Affiliation UCL - FSA/ELEC - Département d'électricité
Links
Bibliographic reference Levacq, D. ; Dessard, V. ; Flandre, Denis. Ultra-low power flip-flops for MTCMOS circuits.IEEE International Symposium on Circuits and Systems (ISCAS) (Kobe, Japan, 23-26 May 2005). In: proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS) (IEEE Cat.No. 05CH37618), IEEE2005, p.Vol. 5, p. 4681-4
Permanent URL http://hdl.handle.net/2078.1/67955