High-performance ultra-low-voltage digital and RF circuits based on adaptive forward back biasing in 28nm FDSOI CMOS

The deployment of the Internet-of-Things ubiquitous sensing paradigm is constrained by the development of the four functions usually embedded in a wireless sensor node: • Power management, targeting efficient energy harvesting from the envi- ronment, conversion and storage. • Sensing, with an emphasis on versatility, energy efficiency and accuracy depending on the targeted application. • Data processing, such as feature extraction or compression, to limit the amount of data to communicate wirelessly. • RF communication, to transmit sensed and processed data to the cloud with high data-rate and low energy per bit. In this work, we explore the design of high-performance ultra-low-voltage (ULV) circuits for both the data processing and the RF communication function with a common objective: the improvement of the energy/performance trade-off. To improve this tradeoff, we rely on innovative digital and analog/RF circuits and systems design as well as on the exploitation of 28nm FDSOI CMOS process. In the last few years, FDSOI technology has emerged as an industrially-proven solution to overcome the limitations of bulk technologies and continue the trend of Moore’s law. In addition to a lower cost compared to FinFet solutions, FDSOI can provide both high-speed or low-leakage solution and is thus an interesting candidate for the implementation of highly-efficient ultra-low-power circuits. Its performances rely on a better electrostatic control of the channel, lower variability, lower parasitic capacitances, lower leakage, steeper subthreshold slope and wide back-biasing range compared to the body-bias range in bulk technology. Among these characteristics, the capability to apply an overdrive back bias voltage above the supply voltage is a key feature of this dissertation. We intend to look at the usefulness of forward back biasing in the design of high performance circuits related to the data processing and RF functionalities of a typical wireless sensor node by looking at three questions: How does FDSOI with its back biasing capability influence the energy/speed tradeoff in ULV digital circuits? How does FDSOI with its back biasing capability influence the power/per- formances in analog/RF circuits? How can the back biasing capability be used to design ULV radios while meeting the specifications of communication standard? As a first step, we study of the impact of back biasing on ultra-low-voltage logic by looking at the evolution of the minimum energy point for several innovative back biasing schemes from gate level to IP level. We show that overdrive forward back biasing helps to extend the design space to higher frequency of operation while keeping minimum energy. Asymmetric adaptive back biasing is presented as a way to mitigate the effect of systematic NMOS/PMOS mismatch on minimum energy point and robustness. At IP level, we prove that mixing two or three overdrive back biasing voltages can be used to reduce the energy per cycle of microcontroller cores over a wide range of frequency of operation. As a second step, we study the performances of 28nm FDSOI with its back biasing capability for analog/RF circuits. A reduction of the supply voltage of RF analog circuits, to ensure compatibility with digital parts or to improve the power consumption, strongly challenges the analog/RF design in nanometer CMOS technologies due to the limited voltage headroom. We show that reducing the supply voltage pushes devices from strong inversion to moderate inversion. Forward back biasing can be used to mitigate this trend and increase the design space. We further show the impact of technology scaling on important RF figure of merits to highlight the ability of 28nm FDSOI to trade speed for power. Then, we illustrate this ability at circuit level with one objective: optimizing a wideband low noise amplifier for the hot topic of software-defined radios. We analyze a wideband LNA to show that technology scaling and forward back biasing shift the minimum supply voltage limitation from the bandwidth constraint to the noise constraint. Finally, we demonstrate the potential of back-biasing in 28nm FDSOI to push digital RF circuits in the ULV domain with a silicon demonstrator: SleepTalker. This chip is an IEEE 802.15.4a ultra-wideband transmitter SoC designed for ultra-low-voltage in 28nm FDSOI CMOS. Operated at 0.55V, it achieves a record energy efficiency of 14pJ/bit with embedded power management, highly duty-cycled digital baseband and programmable pulse shaping for compliance with regulation. A wide-range on-chip adaptive forward back biasing is used for threshold voltage reduction allowing 3.5 to 4.5GHz operation at 0.55V thereby showing that back-biasing can act as an enabler for ultra-low-voltage RF circuits. The forward back biasing is also used for PVT compensation and tuning of both the carrier frequency and the output power which shows how it can be used as a control knob for RF functionality.