Disruptive ultra-low-leakage design techniques for ultra-low-power CMOS circuits

Flandre, Denis [UCL] Bulteel, Olivier [UCL] Gosset, Geoffroy [UCL] Haddad, Pierre-Antoine [UCL] Bernard, Sébastien [UCL] Rue, Bertrand [UCL] Bol, David [UCL]

We introduce a disruptive ultra-low-leakage design technique, based on a pair of source-connected n- and p-MOSFETs, auto-biasing the stand-by gate-to-source voltage of the nMOSFET at negative voltage and that of the p-device at positive, thereby pushing the off current of analog and digital functions towards its physical limits, without reducing functional performance. Therefrom, we designed ultra-low-power basic blocks (2-terminal diode, 3-terminal transistor, voltage follower), circuits (7-transistor SRAM and MTCMOS latch with record low leakage but still high speed), as well as microsystems (e.g. high-frequency power-management units for RF and PV energy harvesting and micro