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Analog performance of asymmetric self-cascode p-channel fully depleted SOI transistors

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De Souza, Michelly [Centro Universitario da FEI] Pavanello, Marcelo Antonio [Centro Universitario da FEI] Flandre, Denis [UCL]

This work presents an analysis of the analog performance of asymmetric threshold voltage self-cascode fully depleted (FD) p-type SOI transistors. The experimental results showed that this structure is able to improve the devices transconductance and output conductance, resulting in increased intrinsic voltage gain and breakdown voltage in comparison to single transistors and the conventional symmetric self-cascode.

Document type Communication à un colloque (Conference Paper) – Présentation orale avec comité de sélection
Publication date 2012
Language Anglais
Conference "8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS 2012)", Playa del Carmen (du 14/03/2012 au 17/03/2012)
Peer reviewed yes
Host document "Proceedings of the 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS 2012)"- 1-4 (ISBN : 978-1-4577-1116-9)
Publisher IEEE
Publication status Publié
Affiliation UCL - SST/ICTM/ELEN - Pôle en ingénierie électrique
Keywords Current measurement ; Logic gates ; Periodic structures ; Threshold voltage ; Transconductance ; Transistors ; Voltage measurement
Links
Bibliographic reference De Souza, Michelly ; Pavanello, Marcelo Antonio ; Flandre, Denis. Analog performance of asymmetric self-cascode p-channel fully depleted SOI transistors.8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS 2012) (Playa del Carmen, du 14/03/2012 au 17/03/2012). In: Proceedings of the 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS 2012), IEEE2012, p.1-4
Permanent URL http://hdl.handle.net/2078.1/114996