Design of an Ultra-Low-Power multi-stage AC/DC voltage rectifier and multiplier using a fully-automated and portable design methodology

A fully-automated and portable design methodology has been developed based on an efficient model and a gradient's method to optimize an ULP (Ultra Low Power) AC-DC multi-stage rectifier through the overall design window in a practical design time. Innovative ULP diodes featuring two CMOS transistors are modeled and used to reduce leakage. The diode model includes parasitic capacitances, thus taking into account DC and AC behavior for various frequencies and voltage amplitudes. A 3-stage rectifier taking a 1 Vpp input sinusoidal signal at 13.56 MHz and providing a 10 μA load current has been designed in 250 nm bulk CMOS technology with 72% power conversion efficiency and 1.99 V output voltage. Robust design decisions with respect to process corner variations have been reached with this methodology and are also presented.