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Low temperature operation of graded-channel SOI nMOSFETs for analog applications

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Pavanello, Marcelo Antonio [Centro Universitario da FEI] Der Agopian, P.G. Martino, Joao Antonio [Centro Universitario da FEI] Flandre, Denis [UCL]

We present in this work is an analysis of the low temperature operation of Graded-Channel fully-depleted Silicon-On-Insulator (SOI) nMOSFETs for analog applications. This analysis is supported by a comparison between the results obtained by MEDICI numerical bidimensional simulations and measurements. The Graded-Channel transistor presents higher Early voltage and transconductance at 100 K if compared to the conventional fullydepleted SOI nMOSFET.

Document type Communication à un colloque (Conference Paper) – Présentation orale avec comité de sélection
Publication date 2002
Language Anglais
Conference "5th European Workshop on Low Temperature Electronics (WOLTE 2002)", Grenoble (France) (du 19/06/2002 au 21/06/2002)
Peer reviewed yes
Host document "Proceedings of the 5th European Workshop on Low Temperature Electronics (WOLTE 2002)"- 23-26 (ISBN : 2-86883-606-2)
Publisher IEEE
Affiliation UCL - FSA/ELEC - Département d'électricité
Keywords Back ; Transconductance ; Capacitance ; Doping ; Intrusion detection ; MOSFETs ; Medical simulation ; Numerical simulation ; Temperature ; Threshold voltage
Links
Bibliographic reference Pavanello, Marcelo Antonio ; Der Agopian, P.G. ; Martino, Joao Antonio ; Flandre, Denis. Low temperature operation of graded-channel SOI nMOSFETs for analog applications.5th European Workshop on Low Temperature Electronics (WOLTE 2002) (Grenoble (France), du 19/06/2002 au 21/06/2002). In: Proceedings of the 5th European Workshop on Low Temperature Electronics (WOLTE 2002), IEEE2002, p.23-26
Permanent URL http://hdl.handle.net/2078.1/113838