User menu

Contribution of carrier tunneling and gate induced drain leakage effects to the gate and drain currents of fin-shaped field-effect transistors

Bibliographic reference Garduno, S.I. ; Cerdeira, A. ; Estrada, M. ; Alvarado, Jose Joaquin ; Kilchytska, Valeriya ; et. al. Contribution of carrier tunneling and gate induced drain leakage effects to the gate and drain currents of fin-shaped field-effect transistors. In: Journal of Applied Physics, Vol. 109, no. 8 (15 avril 2011)
Permanent URL http://hdl.handle.net/2078.1/86363
  1. FinFETs and Other Multi-Gate Transistors, ISBN:9780387717517, 10.1007/978-0-387-71752-4
  2. Rudenko T., Kilchytska V., Collaert N., Jurczak M., Nazarov A., Flandre D., Reduction of gate-to-channel tunneling current in FinFET structures, 10.1016/j.sse.2007.09.016
  3. Yee-Chia Yeo, Tsu-Jae King, Chenming Hu, MOSFET gate leakage modeling and selection guide for alternative gate dielectrics based on leakage considerations, 10.1109/ted.2003.812504
  4. Hoffmann T., IEEE IEDM Technical Digest, 725 (2005)
  5. Tsormpatzoglou A., Dimitriadis C.A., Mouis M., Ghibaudo G., Collaert N., Experimental characterization of the subthreshold leakage current in triple-gate FinFETs, 10.1016/j.sse.2009.01.008
  6. Choi Yang-Kyu, Ha Daewon, King Tsu-Jae, Bokor Jeffrey, Investigation of Gate-Induced Drain Leakage (GIDL) Current in Thin Body Devices: Single-Gate Ultra-Thin Body, Symmetrical Double-Gate, and Asymmetrical Double-Gate MOSFETs, 10.1143/jjap.42.2073
  7. Yuan Xiaobin, Park Jae-Eun, Wang Jing, Zhao Enhai, Ahlgren David C., Hook Terence, Yuan Jun, Chan Victor W. C., Shang Huiling, Liang Chu-Hsin, Lindsay Richard, Park Sungjoon, Choo Hyotae, Gate-Induced-Drain-Leakage Current in 45-nm CMOS Technology, 10.1109/tdmr.2008.2002350
  8. Cerdeira A., Moldovan O., Iñiguez B., Estrada M., Modeling of potentials and threshold voltage for symmetric doped double-gate MOSFETs, 10.1016/j.sse.2007.10.046
  9. Cerdeira Antonio, Iñiguez Benjamín, Estrada Magali, Compact model for short channel symmetric doped double-gate MOSFETs, 10.1016/j.sse.2008.03.009
  10. Wen-Chin Lee, Chenming Hu, Modeling CMOS tunneling currents through ultrathin gate oxide due to conduction- and valence-band electron and hole tunneling, 10.1109/16.930653
  11. Schuegraf K.F., Chenming Hu, Hole injection SiO/sub 2/ breakdown model for very low voltage lifetime extrapolation, 10.1109/16.285029
  12. Register Leonard F., Rosenbaum Elyse, Yang Kevin, Analytic model for direct tunneling current in polycrystalline silicon-gate metal–oxide–semiconductor devices, 10.1063/1.123060
  13. Lee Q., Martin S.C., Mensa D., Smith R.P., Guthrie J., Rodwell M.J.W., Submicron transferred-substrate heterojunction bipolar transistors, 10.1109/55.778155
  14. Lee W.-C., 2000 International Symposium on VLSI Technology, 198 (2000)
  15. Clerc R., O'Sullivan P., McCarthy K.G., Ghibaudo G., Pananakakis G., Mathewson A., A physical compact model for direct tunneling from NMOS inversion layers, 10.1016/s0038-1101(01)00220-9
  16. Clerc R., Ghibaudo G., Pananakakis G., Bardeen's approach for tunneling evaluation in MOS structures, 10.1016/s0038-1101(02)00039-4
  17. Yang L, Asenov A, Watling J.R, Boriçi M, Barker J.R, Roy S, Elgaid K, Thayne I, Hackbarth T, Impact of device geometry and doping strategy on linearity and RF performance in Si/SiGe MODFETs, 10.1016/j.microrel.2004.04.003
  18. Mondal Imon, Dutta Aloke K., An Analytical Gate Tunneling Current Model for MOSFETs Having Ultrathin Gate Oxides, 10.1109/ted.2008.924443
  19. Yee Chia Yeo, Qiang Lu, Wen Chin Lee, Tsu-Jae King, Chenming Hu, Xiewen Wang, Xin Guo, Ma T.P., Direct tunneling gate leakage current in transistors with ultrathin silicon nitride gate dielectric, 10.1109/55.877204
  20. Robertson J., Band structures and band offsets of high K dielectrics on Si, 10.1016/s0169-4332(01)00832-7
  21. Engström O., Will the Insulated Gate Transistor Concept Survive Next Decade? Future Trends in Microelectronics: Up the Nano Creek (2007)
  22. Wilk G. D., Wallace R. M., Electrical properties of hafnium silicate gate dielectrics deposited directly on silicon, 10.1063/1.124036
  23. Gurfinkel Moshe, Suehle John S., Shapira Yoram, Enhanced gate induced drain leakage current in HfO2 MOSFETs, 10.1016/j.mee.2009.02.029
  24. Kauerauf Thomas, Govoreanu Bogdan, Degraeve Robin, Groeseneken Guido, Maes Herman, Scaling CMOS: Finding the gate stack with the lowest leakage current, 10.1016/j.sse.2005.01.018