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A real-time VLSI-based architecture for multi-motion estimation

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Legat, Jean-Didier [UCL] Cornil, J.P. Macq, D. Verleysen, Michel [UCL]

This paper describes a new parallel architecture dedicated to multi-motion estimation. The input image is scanned by a standard video camera with 256 grey levels. Motion computing is based on the optical flow determination. Some constraints are proposed to allow multi-motion evaluation. The algorithm is presented and the main features of a 1-D systolic architecture which is based on a custom VLSI chip is given. This architecture allows a real-time implementation of the multi-motion estimation algorithm.

Document type Communication à un colloque (Conference Paper) – Présentation orale avec comité de sélection
Publication date 1992
Language Anglais
Conference "Proceedings. 11th IAPR International Conference on Pattern Recognition. Vol. IV. Conference D: Architectures for Vision and Pattern Recognition", The Hague, Netherlands (30 August-3 September 1992)
Peer reviewed yes
Host document "Proceedings. 11th IAPR International Conference on Pattern Recognition.Vol. IV. Conference D: Architectures for Vision and Pattern Recognition"- p. 147-150 (ISBN : 0-8186-2925-8)
Publisher IEEE comput. soc. press
Affiliation UCL - FSA/ELEC - Département d'électricité
Links
Bibliographic reference Legat, Jean-Didier ; Cornil, J.P. ; Macq, D. ; Verleysen, Michel. A real-time VLSI-based architecture for multi-motion estimation.Proceedings. 11th IAPR International Conference on Pattern Recognition. Vol. IV. Conference D: Architectures for Vision and Pattern Recognition (The Hague, Netherlands, 30 August-3 September 1992). In: Proceedings. 11th IAPR International Conference on Pattern Recognition.Vol. IV. Conference D: Architectures for Vision and Pattern Recognition, IEEE comput. soc. press1992, p. 147-150
Permanent URL http://hdl.handle.net/2078.1/68276