Accès à distance ? S'identifier sur le proxy UCLouvain
Improved synthesis of gain-boosted regulated-cascode CMOS stages using symbolic analysis and gm/ID methodology
Primary tabs
Document type | Communication à un colloque (Conference Paper) – Présentation orale avec comité de sélection |
---|---|
Publication date | 1997 |
Language | Anglais |
Conference | "22nd European Solid-State Circuits Conference (ESSCIRC 96)", Neufchâtel (Switzerland) (du 17/09/1996 au 19/09/1997) |
Journal information | "IEEE Journal of Solid State Circuits" - Vol. 32, no. 7, p. 1006-1012 (1997) |
Peer reviewed | yes |
issn | 0018-9200 |
e-issn | 1558-173X |
Host document | "Proceedings of the 22nd European Solid-State Circuits Conference (ESSCIRC 96)" |
Publisher | Ieee-inst Electrical Electronics Engineers Inc (New York) |
Affiliations |
UCL UCL - Autre |
Keywords | Circuit Stability ; Circuit Synthesis ; Cmos Analog Integrated Circuits ; Design Automation ; Operational Amplifiers ; Silicon-on-insulator Technology |
Links |
Bibliographic reference | Flandre, Denis ; Viviani, A ; Eggermont, JP. ; Gentinne, B. ; Jespers, PGA.. Improved synthesis of gain-boosted regulated-cascode CMOS stages using symbolic analysis and gm/ID methodology.22nd European Solid-State Circuits Conference (ESSCIRC 96) (Neufchâtel (Switzerland), du 17/09/1996 au 19/09/1997). In: IEEE Journal of Solid State Circuits, Vol. 32, no. 7, p. 1006-1012 (1997)In: Proceedings of the 22nd European Solid-State Circuits Conference (ESSCIRC 96), Ieee-inst Electrical Electronics Engineers Inc : New York1997 |
---|---|
Permanent URL | http://hdl.handle.net/2078.1/62740 |