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SOI technology for future high-performance smart cards

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Neve, Amaury [UCL] Quisquater, Jean-Jacques [UCL] Flandre, Denis [UCL]

Chips based on silicon-on-insulator technology meet the tough performance and security requirements presented by smart cards. A test chip manufactured in a fully depleted SOI process incorporates a charge pump and random-number generator, critical smart-card circuit blocks.

Document type Communication à un colloque (Conference Paper) – Présentation orale avec comité de sélection
Publication date 2003
Language Anglais
Conference "Workshop on Electronics in the 21st Century: Trends and Challenges", Rome (Italy)
Journal information "IEEE Micro" - Vol. 23, no. 3, p. 58-67 (2003)
Peer reviewed yes
issn 0272-1732
e-issn 1937-4143
Host document "Proceedings of the Workshop on Electronics in the 21st Century: Trends and Challenges"
Publisher Ieee Computer Soc (Los Alamitos)
Publication status Publié
Affiliation UCL - FSA/ELEC - Département d'électricité
Keywords CMOS integrated circuits ; random number generation ; silicon-on-insulator ; smart cards
Links
Bibliographic reference Neve, Amaury ; Quisquater, Jean-Jacques ; Flandre, Denis. SOI technology for future high-performance smart cards.Workshop on Electronics in the 21st Century: Trends and Challenges (Rome (Italy)). In: IEEE Micro, Vol. 23, no. 3, p. 58-67 (2003)In: Proceedings of the Workshop on Electronics in the 21st Century: Trends and Challenges, Ieee Computer Soc : Los Alamitos2003
Permanent URL http://hdl.handle.net/2078.1/61546