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Cryogenic operation of graded-channel silicon-on-insulator nMOSFETs for high performance analog applications

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Pavanello, MA Flandre, Denis [UCL] Der Agopian, PG Martino, JA

We present in this work an analysis of the low temperature operation of Graded-Channel fully depleted Silicon-On-Insulator (Sol) nMOSFETs for analog applications, in the range of 100-300 K. This analysis is supported by a comparison between the results obtained by two-dimensional numerical simulations and measurements in the whole temperature range under study. The Graded-Channel transistor presents higher Early voltage if compared to the conventional fully depleted Sol nMOSFET, without degrading the transconductance over drain current, at all studied temperatures, leading to a gain larger than 20 dB compared to the conventional SOL The resulting higher gain lies in the improvement of the electric field distribution and impact ionization rate by the graded-channel structure. (C) 2005 Elsevier Ltd. All rights reserved.

Document type Article de périodique (Journal article) – Article de recherche
Access type Accès restreint
Publication date 2006
Language Anglais
Journal information "Microelectronics" - Vol. 37, no. 2, p. 137-144 (2006)
Peer reviewed yes
Publisher Elsevier Sci Ltd (Oxford)
issn 0026-2692
Publication status Publié
Affiliation UCL - FSA/ELEC - Département d'électricité
Keywords silicon-on-insulator ; channel engineering ; graded-channel ; analog circuits ; low temperature
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Bibliographic reference Pavanello, MA ; Flandre, Denis ; Der Agopian, PG ; Martino, JA. Cryogenic operation of graded-channel silicon-on-insulator nMOSFETs for high performance analog applications. In: Microelectronics, Vol. 37, no. 2, p. 137-144 (2006)
Permanent URL http://hdl.handle.net/2078.1/38706