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Back-gate bias Effect on the MOSFET-C CMOS UTBB Performance by Circuit Simulations

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Martínez, A. [Benemérita Universidad Autónoma de Puebla, CIDS, Av. San Claudio y 18 Sur, Col. San Manuel, Ciudad Universitaria, CP 72570, P.O. Box 1067, Puebla, Pue., 7200, Mexico] Alvarado, J. [Benemérita Universidad Autónoma de Puebla, CIDS, Av. San Claudio y 18 Sur, Col. San Manuel, Ciudad Universitaria, CP 72570, P.O. Box 1067, Puebla, Pue., 7200, Mexico] Kilchytska, Valeriya [UCL] Alcántara, S. [Benemérita Universidad Autónoma de Puebla, CIDS, Av. San Claudio y 18 Sur, Col. San Manuel, Ciudad Universitaria, CP 72570, P.O. Box 1067, Puebla, Pue., 7200, Mexico] Flandre, Denis [UCL]

This work investigates the on-resistance and harmonic distortion (HD) of Ultra-Thin Body and Buried Oxide (UTBB) fully-depleted (FD) Silicon-on-Insulator (SOI) MOSFETs for a typical process (TT) working in the triode regime, of interest for MOSFET-C filter applications. Circuit simulations of the DC characteristics of n- and p-type MOSFETs in a large temperature range (-25ºC–150ºC) allow to identify the interest of the back-gate bias to compensate the shift of the on-resistance and 3rd - order HD with the temperature.

Document type Communication à un colloque (Conference Paper) – Présentation orale avec comité de sélection
Access type Accès libre
Publication date 2019
Language Anglais
Conference "5th joint EUROSOI – ULIS 2019 Conference ", Grenoble (France) (04/2019)
Peer reviewed yes
Affiliation UCL - SST/ICTM/ELEN - Pôle en ingénierie électrique
Keywords UTBB-FDSOI; Harmonic Distortion; MOSFET-C filter
Links
Bibliographic reference Martínez, A. ; Alvarado, J. ; Kilchytska, Valeriya ; Alcántara, S. ; Flandre, Denis. Back-gate bias Effect on the MOSFET-C CMOS UTBB Performance by Circuit Simulations .5th joint EUROSOI – ULIS 2019 Conference (Grenoble (France), 04/2019).
Permanent URL http://hdl.handle.net/2078.1/259856