Stas, François
[UCL]
Bol, David
[UCL]
Ultra-low-voltage (ULV) operation of logic circuits is an interesting solution to reduce power consumption in digital circuits. However the always-on blocks at nominal Vdd are necessary for functionality or I/O communications, which induces complex timing closure. In this paper, we propose a 5.4fJ/cycle 0.4V to 1.2V level-shifting flip-flop in 28nm FDSOI, which simplifies the clock tree constraints between the power domains.
Bibliographic reference |
Stas, François ; Bol, David. Integration of Level Shifting in a TSPC Flip-Flop for Low-Power Robust Timing Closure in Dual-Vdd ULV Circuits.2017 IEEE International Circuits and Systems Conference (ISCAS 2017) (Baltimore (USA), du 28/05/2017 au 31/05/2017). |
Permanent URL |
http://hdl.handle.net/2078.1/189103 |