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Integration of Level Shifting in a TSPC Flip-Flop for Low-Power Robust Timing Closure in Dual-Vdd ULV Circuits

Bibliographic reference Stas, François ; Bol, David. Integration of Level Shifting in a TSPC Flip-Flop for Low-Power Robust Timing Closure in Dual-Vdd ULV Circuits.2017 IEEE International Circuits and Systems Conference (ISCAS 2017) (Baltimore (USA), du 28/05/2017 au 31/05/2017).
Permanent URL http://hdl.handle.net/2078.1/189103