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Use of back gate bias to enhance the analog performance of planar FD and UTBB SOI transistors-based self-cascode structures

Bibliographic reference Dorai, R.T. ; Flandre, Denis ; Trevisoli, R. ; de Souza, Michelly ; Pavanelo, Marcelo Antonio. Use of back gate bias to enhance the analog performance of planar FD and UTBB SOI transistors-based self-cascode structures.2015 30th Symposium on Microelectronics Technology and Devices (SBMicro) (Salvador, du 31/08/2015 au 04/09/2015). In: Proceedings of SBMicro 2015, 2015
Permanent URL http://hdl.handle.net/2078.1/171039