Dorai, R.T.
[Electr. Eng. Dept., Centro universitario da FEI, Brazil]
Flandre, Denis
[UCL]
Trevisoli, R.
[Electr. Eng. Dept., Centro universitario da FEI, Brazil]
de Souza, Michelly
[Electr. Eng. Dept., Centro universitario da FEI, Brazil]
Pavanelo, Marcelo Antonio
[Electr. Eng. Dept., Centro universitario da FEI, Brazil]
This paper reports, for the first time, the use of back gate bias to improve the intrinsic voltage gain of self-cascode structures composed by planar FD and UTBB SOI MOSFETs. It is shown a voltage gain improvement larger than 10 dB when either a forward back bias is applied to the drain-side transistor or a reverse back bias is applied to the source side device.
Bibliographic reference |
Dorai, R.T. ; Flandre, Denis ; Trevisoli, R. ; de Souza, Michelly ; Pavanelo, Marcelo Antonio. Use of back gate bias to enhance the analog performance of planar FD and UTBB SOI transistors-based self-cascode structures.2015 30th Symposium on Microelectronics Technology and Devices (SBMicro) (Salvador, du 31/08/2015 au 04/09/2015). In: Proceedings of SBMicro 2015, 2015 |
Permanent URL |
http://hdl.handle.net/2078.1/171039 |