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OCTO Layout Variations as an Alternative to Mitigate TID Effects

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Fino, Leonardo Navarenho de Souza [Department of Electrical Engineering, Centro Universitario da FEI, Brazil] da Silveira, M.A.G. [Department of Physics, Centro Universitario da FEI, Brazil] Renaux, Christian [UCL] Flandre, Denis [UCL] Gimenez, Salvador Pinillos [Department of Electrical Engineering, Centro Universitario da FEI, Brazil]

This paper performs an experimental comparative study between the OCTO SOI MOSFET (octagonal gate geometry) and its derivations (different angles) as a total ionizing dose (TID) effects mitigation strategy. After a TID equal a 600 krad were analyzed the leakage current (ILEAK) behaviour in order to indicate the better configuration for digital applications in radioactive environment. The α angle equal to 53.1° achieved promising resultsfor low power and low voltage applications due ILEAK reduction in function of the TID.

Document type Communication à un colloque (Conference Paper) – Présentation orale avec comité de sélection
Access type Accès restreint
Publication date 2015
Language Anglais
Conference "10th Workshop on Semiconductors and Micro & Nano Technology (SEMINATEC 2015)", Sao Bernardo do Campo (Brazil) (du 09/04/2015 au 10/04/2015)
Peer reviewed yes
Host document
Publication status Publié
Affiliation UCL - SST/ICTM/ELEN - Pôle en ingénierie électrique
Keywords OCTO SOI MOSFET ; Octogonal gate geometry ; TID ; Total ionizing dose
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Bibliographic reference Fino, Leonardo Navarenho de Souza ; da Silveira, M.A.G. ; Renaux, Christian ; Flandre, Denis ; Gimenez, Salvador Pinillos. OCTO Layout Variations as an Alternative to Mitigate TID Effects.10th Workshop on Semiconductors and Micro & Nano Technology (SEMINATEC 2015) (Sao Bernardo do Campo (Brazil), du 09/04/2015 au 10/04/2015).
Permanent URL http://hdl.handle.net/2078.1/167803