User menu

Accès à distance ? S'identifier sur le proxy UCLouvain

Silicon-on-insulator MOSFETs models in analog/RF domain

Primary tabs

Raskin, Jean-Pierre [UCL]

Several physical phenomena specific to silicon-on-insulator metal-oxide-semiconductor field-effect transistors, such as floating body effects, self-heating, and substrate coupling, are described and modeled. Small-signal equivalent circuit of ultra-thin body and thin buried oxide and fin field effect transistor (FinFET) are extracted, and their radio frequency figures of merit as well as their advantages and limitations are presented. We demonstrate the importance of performing wideband characterization at the early stage of the technology development in order to identify the device weaknesses and come up with technological solutions to overcome those. With the ongoing downscaling of the metal-oxide-semiconductor devices, the surrounding of the transistor, that is, the contacts, the access lines, and the substrate, starts to play a major role on the transistor behavior. There is an urgent need to develop adequate models for the new generation of devices valid over a wide frequency band. © (2013) The Authors. INTERNATIONAL JOURNAL OF NUMERICAL MODELLING: ELECTRONIC NETWORKS, DEVICES AND FIELDS Published by.

Document type Article de périodique (Journal article) – Article de recherche
Access type Accès restreint
Publication date 2014
Language Anglais
Journal information "International Journal of Numerical Modelling: Electronic Networks, Devices and Fields" - Vol. 27, no. 5-6, p. 707-735 (2014)
Peer reviewed yes
Publisher JohnWiley & Sons Ltd.
e-issn 1099-1204
issn 0894-3370
Publication status Publié
Affiliation UCL - SST/ICTM/ELEN - Pôle en ingénierie électrique
Links
  1. Moore, Electronics, 38, 114 (1965)
  2. Dennard R.H., Gaensslen F.H., Rideout V.L., Bassous E., LeBlanc A.R., Design of ion-implanted MOSFET's with very small physical dimensions, 10.1109/jssc.1974.1050511
  3. Smith P.M., Liu S.-M.J., Kao M.-Y., Ho P., Wang S.C., Duh K.H.G., Fu S.T., Chao P.C., W-band high efficiency InP-based power HEMT with 600 GHz f/sub max/, 10.1109/75.392284
  4. Rodwell M.J.W., Urteaga M., Mathew T., Scott D., Mensa D., Lee Q., Guthrie J., Betser Y., Martin S.C., Smith R.P., Jaganathan S., Krishnan S., Long S.I., Pullela R., Agarwal B., Bhattacharya U., Samoska L., Dahlstrom M., Submicron scaling of HBTs, 10.1109/16.960387
  5. Lai R Mei XB Deal WR Yoshida W Kim YM Liu PH Lee J Uyeda J Radisic V Lange M Gaier T Samoska L Fung A Sub 50 nm InP HEMT device with Fmax greater than 1 THz IEEE International Electron Devices Meeting - IEDM 2007 2007 609 611
  6. Lee S Jagannathan B Narasimha S Chou A Zamdmer N Johnson J Williams R Wagner L Kim J Plouchart J-O Pekarik J Springer S Freeman G Record RF performance of 45-nm SOI CMOS technology IEEE International Electron Devices Meeting - IEDM 2007 2007 255 258
  7. Sakurai, Fully-Depleted SOI CMOS Circuits and Technology for Ultralow-Power Applications, XV (2006)
  8. Raskin J.-P., Viviani A., Flandre D., Colinge J.-P., Substrate crosstalk reduction using SOI technology, 10.1109/16.644646
  9. Dambrine G., Cappy A., Heliodore F., Playez E., A new method for determining the FET small-signal equivalent circuit, 10.1109/22.3650
  10. Lee S., Yu H.K., Kim C.S., Koo J.G., Nam K.S., A novel approach to extracting small-signal model parameters of silicon MOSFET's, 10.1109/75.556037
  11. Raskin J.P., Dambrine G., Gillon R., Direct extraction of the series equivalent circuit parameters for the small-signal model of SOI MOSFETs, 10.1109/75.645191
  12. Raskin J.-P., Gillon R., Jian Chen, Vanhoenacker-Janvier D., Colinge J.-P., Accurate SOI MOSFET characterization at microwave frequencies for device performance optimization and analog modeling, 10.1109/16.669514
  13. Raskin Jean-Pierre, Wideband characterization of SOI materials and devices, 10.1016/j.sse.2007.07.014
  14. Tinoco, Int J Numer Modell, 23, 107 (2010)
  15. Tinoco J.C., Martinez-Lopez A.G., Raskin J.-P., Mobility degradation and transistor asymmetry impact on field effect transistor access resistances extraction, 10.1016/j.sse.2010.10.020
  16. Tihanyi Jenö, Schlötterer Heinrich, Influence of the floating substrate potential on the characteristics of ESFI MOS transistors, 10.1016/0038-1101(75)90083-0
  17. Pretet J Matsumoto T Cristoloveanu S Gwoziecki R Raynaud C Roveda A Brut H New mechanism of body charging in partially depleted SOI MOSFETs with ultra-thin gate oxides Proc. ESSDERC 2002 515 518
  18. Mercha A., Rafi J.M., Simoen E., Augendre E., Claeys C., "Linear kink effect" induced by electron valence band tunneling in ultrathin gate oxide bulk and SOI MOSFETs, 10.1109/ted.2003.814983
  19. Okhonin S., Nagoga M., Sallese J.M., Fazan P., A capacitor-less 1T-DRAM cell, 10.1109/55.981314
  20. Colinge Jean-Pierre, Silicon-on-Insulator Technology: Materials to VLSI, ISBN:9781461347958, 10.1007/978-1-4419-9106-5
  21. Lederer Dimitri, Raskin Jean-Pierre, Characterization of the Body Node in PD SOI MOSFETs Using Multiport VNA Measurements, 10.1109/ted.2007.907188
  22. Ying-Che Tseng, Huang W.M., Monk D.J., Welch P., Ford J.M., Woo J.C.S., AC floating body effects and the resultant analog circuit issues in submicron floating body and body-grounded SOI MOSFET's, 10.1109/16.777157
  23. Lederer Dimitri, Flandre Denis, Raskin Jean-Pierre, High frequency degradation of body-contacted PD SOI MOSFET output conductance, 10.1088/0268-1242/20/5/025
  24. Dehan Morin, Raskin Jean-Pierre, Dynamic threshold voltage MOS in partially depleted SOI technology: a wide frequency band analysis, 10.1016/j.sse.2004.07.003
  25. Lederer D Rozeau O Raskin J-P Wideband characterization of body-accessed PD SOI MOSFETs with multiport measurements IEEE International SOI Conference 2005 65 66
  26. www-device.eecs.berkeley.edu/~bsimsoi
  27. Bracale A., Ferlet-Cavrois V., Fel N., Pasquet D., Gautier J. L., Pelloie J. L., du Port de Poncharra J., 10.1023/a:1008332732738
  28. Su P Fung S Liu W Hu C Studying the impact of gate tunneling on dynamic behaviors of partially-depleted SOI CMOS using BSIMPD IEEE 2002 International Symposium on Quality Electronic Design 2002 487 491
  29. Joshi RV Chuang CT Fung SKH Assaderaghi F Sherony M Yang I Shahidi G Effects of gate-to-body tunneling current on PD/SOI CMOS SRAM 2001 Symposium on VLSI Technology 2001 75 76
  30. Lederer D., Flandre D., Raskin J.-P., AC Behavior of Gate-Induced Floating Body Effects in Ultrathin Oxide PD SOI MOSFETs, 10.1109/led.2003.822658
  31. Skotnicki T., Fenouillet-Beranger C., Gallon C., Boeuf F., Monfray S., Payet F., Pouydebasque A., Szczap M., Farcy A., Arnaud F., Clerc S., Sellier M., Cathignol A., Schoellkopf J.-P., Perea E., Ferrant R., Mingam H., Innovative Materials, Devices, and CMOS Technologies for Low-Power Mobile Multimedia, 10.1109/ted.2007.911338
  32. International Technology Roadmap for Semiconductor (ITRS), 2011 Edition www.itrs.com
  33. Leland Chang, Yang-Kyu Choi, Daewon Ha, Ranade P., Shiying Xiong, Bokor J., Chenming Hu, Tsu-Jae King, Extremely scaled silicon nano-CMOS devices, 10.1109/jproc.2003.818336
  34. Yang-Kyu Choi, Asano K., Lindert N., Subramanian V., Tsu-Jae King, Bokor J., Chenming Hu, Ultrathin-body SOI MOSFET for deep-sub-tenth micron era, 10.1109/55.841313
  35. Sugii N Tsuchiya R Ishigaki T Morita Y Yoshimoto H Kazuyoshi T Kimura S Comprehensive study on V th variability in silicon on thin BOX (SOTB) CMOS with small random-dopant fluctuation: finding a way to further reduce variation IEEE Electron Devices Meeting (IEDM) 2008 1 4
  36. Ohtou T., Sugii N., Hiramoto T., Impact of Parameter Variations and Random Dopant Fluctuations on Short-Channel Fully Depleted SOI MOSFETs With Extremely Thin BOX, 10.1109/led.2007.901276
  37. Fenouillet-Beranger C., Skotnicki T., Monfray S., Carriere N., Boeuf F., Requirements for ultra-thin-film devices and new materials for the CMOS roadmap, 10.1016/j.sse.2003.12.039
  38. Fenouillet-Beranger C Skotnicki T Monfray S Carriere N Boeuf F Requirements for ultra-thin-film devices and new materials on CMOS roadmap Proc. IEEE International SOI Conference 2003 145 146
  39. Mazellier JP Andrieu F Faynot O Brevard L Buj C Christoloveanu S Le Tiec Y Deleonibus S Threshold voltage in ultra-thin FD SOI CMOS: advanced triple interface model and experimental devices Proc. Ultimate Integration on Silicon (ULIS) 1 2008 31 34
  40. Burignat S., Flandre D., Md Arshad M.K., Kilchytska V., Andrieu F., Faynot O., Raskin J.-P., Substrate impact on threshold voltage and subthreshold slope of sub-32nm ultra thin SOI MOSFETs with thin buried oxide and undoped channel, 10.1016/j.sse.2009.12.021
  41. Fenouillet-Beranger C Thomas O Perreau P Noel JP Bajolet A Haendler S Tosti L Barnola S Beneyton R Perrot C de Buttet C Abbate F Baron F Pernet B Campidelli Y Pinzelli L Gouraud P Cassé M Borowiak C Weber O Andrieu F Denorme S Boeuf F Faynot O Skotnicki T Bourdelle KK Nguyen B-Y Boedt F Efficient multi-V T FD SOI technology with UTBOX for low power circuit design IEEE Symposium on VLSI Technology (VLSIT) 2010 65 66
  42. Fenouillet-Beranger C., Denorme S., Perreau P., Buj C., Faynot O., Andrieu F., Tosti L., Barnola S., Salvetat T., Garros X., Cassé M., Allain F., Loubet N., Pham-Nguyen L., Deloffre E., Gros-Jean M., Beneyton R., Laviron C., Marin M., Leyris C., Haendler S., Leverd F., Gouraud P., Scheiblin P., Clement L., Pantel R., Deleonibus S., Skotnicki T., FDSOI devices with thin BOX and ground plane integration for 32nm node and below, 10.1016/j.sse.2009.02.009
  43. Fenouillet-Beranger C., Perreau P., Denorme S., Tosti L., Andrieu F., Weber O., Monfray S., Barnola S., Arvet C., Campidelli Y., Haendler S., Beneyton R., Perrot C., de Buttet C., Gros P., Pham-Nguyen L., Leverd F., Gouraud P., Abbate F., Baron F., Torres A., Laviron C., Pinzelli L., Vetier J., Borowiak C., Margain A., Delprat D., Boedt F., Bourdelle K., Nguyen B.-Y., Faynot O., Skotnicki T., Impact of a 10nm ultra-thin BOX (UTBOX) and ground plane on FDSOI devices for 32nm node and below, 10.1016/j.sse.2010.04.009
  44. Thomas O Noel JP Fenouillet-Beranger C Jaud MA Dura J Perreau P Boeuf F Andrieu F Delprat D Boedt F Bourdelle K Nguyen B-Y Vladimirescu A Amara A 32 nm and beyond multi-V T ultra-thin body and BOX FD SOI: from device to circuit International Symposium on Circuits and Systems (ISCAS) 2010 1703 1706
  45. Arshad MKMd Kilchytska V Makovejev S Olsen S Andrieu F Raskin J-P Flandre D UTBB SOI MOSFETs analog figures of merit: effect of ground plane and asymmetric double-gate regime Eighth Workshop of the Thematic Network on Silicon on Insulator technology, devices and circuits - EuroSOI'12 2012 111 112
  46. Arshad, Solid State Electron (2013)
  47. Kilchytska V., Md Arshad M.K., Makovejev S., Olsen S., Andrieu F., Poiroux T., Faynot O., Raskin J.-P., Flandre D., Ultra-thin body and thin-BOX SOI CMOS technology analog figures of merit, 10.1016/j.sse.2011.11.020
  48. Dambrine G., Raynaud C., Lederer D., Dehan M., Rozeaux O., Vanmackelberg M., Danneville F., Lepilliet S., Raskin J.-P., What are the limiting parameters of deep-submicron MOSFETs for high frequency applications?, 10.1109/led.2003.809525
  49. Lim T Rozeau O Buj C Paccaud M Dambrine G Danneville F HF characterisation of sub-100 nm UTB-FDSOI with TiN/HfO 2 gate stack Proc. Ultimate Integration on Silicon (ULIS) 2008 145 148
  50. Khakifirooz A Cheng K Kulkarni P Challenges and opportunities of extremely thin SOI (ETSOI) CMOS technology for future low power and general purpose system-on-chip applications Proc. VLSI Technology, System and Applications 2010 110 111
  51. Balestra F., Cristoloveanu S., Benachir M., Brini J., Elewa T., Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance, 10.1109/edl.1987.26677
  52. Chenming Hu, Bokor J., Tsu-Jae King, Anderson E., Kuo C., Asano K., Takeuchi H., Kedzierski J., Wen-Chin Lee, Hisamoto D., FinFET-a self-aligned double-gate MOSFET scalable to 20 nm, 10.1109/16.887014
  53. Cristoloveanu Sorin, Silicon on insulator technologies and devices: from present to future, 10.1016/s0038-1101(00)00271-9
  54. Jong-Tae Park, Colinge J.-P., Multiple-gate SOI MOSFETs: device design guidelines, 10.1109/ted.2002.805634
  55. Kedzierski J Fried DM Nowak EJ Kanarsky T Rankin V Hanafi H Natzle W Boyd D Zhang Y Roy RA Newbury J Yu C Yang Q Saunders P Willets CP Johnson A Cole SP Young HE Carpenter N Rakowski D Rainey BA Cottrell PE Ieong M Wong H-SPM et al High performance symmetric-gate and CMOS-compatible Vt asymmetric-gate FinFET devices IEEE International Electron Devices Meeting - IEDM 2001 2001 437 440
  56. Dong-Soo Woo, Jong-Ho Lee, Woo Young Choi, Byung-Yong Choi, Young-Jin Choi, Jong Duk Lee, Byung-Gook Park, Electrical characteristics of FinFET with vertically nonuniform source/drain doping profile, 10.1109/tnano.2002.807373
  57. Kilchytska V Collaert N Rooyackers R Lederer D Raskin J-P Flandre D Perspective of FinFETs for analog applications 34 th European Solid-State Device Research Conference - ESSDERC 2004 2004 65 68
  58. Lederer D., Kilchytska V., Rudenko T., Collaert N., Flandre D., Dixit A., De Meyer K., Raskin J.-P., FinFET analogue characterization from DC to 110GHz, 10.1016/j.sse.2005.07.011
  59. Raskin, J Telecommun Inf Tech, 4, 3 (2009)
  60. Dixit A., Kottantharayil A., Collaert N., Goodwin M., Jurczak M., DeMeyer K., DeMeyer K., Analysis of the Parasitic S/D Resistance in Multiple-Gate FETs, 10.1109/ted.2005.848098
  61. Razavi B., Ran-Hong Yan, Lee K.F., Impact of distributed gate resistance on the performance of MOS devices, 10.1109/81.331530
  62. Wu Wen, Chan Mansun, Analysis of Geometry-Dependent Parasitics in Multifin Double-Gate FinFETs, 10.1109/ted.2007.891252
  63. Kranti A Raskin J-P Armstrong GA Optimizing FinFET geometry and parasitics for RF applications IEEE International SOI Conference, SOI'2008 2008 123 124
  64. Lederer D Parvais B Mercha A Collaert N Jurczak M Raskin J-P Decoutere S Dependence of FinFET RF performance on fin width The 6 th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems - SiRF'06 2006 8 11
  65. Subramanian Vaidyanathan, Mercha Abdelkarim, Parvais Bertrand, Dehan Morin, Groeseneken Guido, Sansen Willy, Decoutere Stefaan, Identifying the Bottlenecks to the RF Performance of FinFETs, 10.1109/vlsi.design.2010.19
  66. Yang X., Maitra K., Yeh C., Zeitzoff P., Raymond M., Kulkarni P., Wang M., Yamashita T., Basker V. S., Standaert T. E., Samavedam S., Bu H., Miller R. J., Analysis of parasitic resistance in double gate FinFETs with different fin lengths, 10.1109/soi.2011.6081799
  67. Tinoco Julio C., Salas Rodriguez Silvestre, Martinez-Lopez Andrea G., Alvarado Joaquín, Raskin Jean-Pierre, Impact of Extrinsic Capacitances on FinFET RF Performance, 10.1109/tmtt.2012.2231697
  68. Salas S Tinoco JC Martinez-Lopez AG Alvarado J Raskin J-P Fringing gate capacitance model for triple-gate FinFET 13 th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems - SiRF'13 2013
  69. Crupi Giovanni, Schreurs Dominique M.M.-P., Raskin Jean-Pierre, Caddemi Alina, A comprehensive review on microwave FinFET modeling for progressing beyond the state of art, 10.1016/j.sse.2012.10.015
  70. Tenbroek B.M., Lee M.S.L., Redman-White W., Bunyan J.T., Uren M.J., Self-heating effects in SOI MOSFETs and their measurement by small signal conductance techniques, 10.1109/16.544417
  71. Pop E., Sinha S., Goodson K.E., Heat Generation and Transport in Nanometer-Scale Transistors, 10.1109/jproc.2006.879794
  72. Wei Jin, Weidong Liu, Fung S.K.H., Chan P.C.H., Chenming Hu, SOI thermal impedance extraction methodology and its significance for circuit simulation, 10.1109/16.915707
  73. Kolluri S Endo K Suzuki E Banerjee K Modeling and analysis of self-heating in FinFET devices for improved circuit and EOS/ESD performance IEEE International Electron Devices Meeting - IEDM 2007 177 180
  74. Molzer W Schulz T Xiong W Cleavelin RC Schrufer K Marshall A Matthews K Sedlmeir J Siprak D Knoblinger G Bertolissi L Patruno P Colinge J-P Self heating simulation of multi-gate FETs Proceedings of the 36 th European Solid-State Device Research Conference - ESSDERC 2006 311 314
  75. Braccioli M., Curatola G., Yang Y., Sangiorgi E., Fiegna C., Simulation of self-heating effects in different SOI MOS architectures, 10.1016/j.sse.2008.09.020
  76. Scholten AJ Smit GDJ Pijper RMT Tiemeijer LF Tuinhout HP van der Steen J-LPJ Mercha A Braccioli M Klaassen DBM Experimental assessment of self-heating in SOI FinFETs IEEE International Electron Devices Meeting - IEDM 2009 305 308
  77. Braccioli M Scholten A Curatola G Sangiorgi E Fiegna C AC and DC numerical simulation of selfheating effects in FinFETs Ultimate Integration on Silicon - ULIS 2010 2010 81 84
  78. Makovejev Sergej, Olsen Sarah, Raskin Jean-Pierre, RF Extraction of Self-Heating Effects in FinFETs, 10.1109/ted.2011.2162333
  79. Makovejev S., Raskin J.-P., Md Arshad M.K., Flandre D., Olsen S., Andrieu F., Kilchytska V., Impact of self-heating and substrate effects on small-signal output conductance in UTBB SOI MOSFETs, 10.1016/j.sse.2011.10.027
  80. Rinaldi N., Small-signal operation of semiconductor devices including self-heating, with application to thermal characterization and instability analysis, 10.1109/16.902734
  81. Kilchytska V., Flandre D., Raskin J.-P., Silicon-on-Nothing MOSFETs: An efficient solution for parasitic substrate coupling suppression in SOI devices, 10.1016/j.apsusc.2008.02.171
  82. Kilchytska V., Levacq D., Lederer D., Raskin J.-P., Flandre D., Floating effective back-gate effect on the small-signal output conductance of SOI MOSFETs, 10.1109/led.2003.813373
  83. Andrieu F Weber O Mazurier J Thomas O Noel J-P Fenouillet-Béranger C Mazellier J-P Perreau P Poiroux T Morand Y Morel T Allegret S Loup V Barnola S Martin F Damlencourt JF Servin I Casse M Garros V Rozeau O Jaud M-A Cibrario G Cluzel J Toffoli A Allain F Kies R Lafond D Delaye V Tabone C Tosti L Brevard L Gaud P Paruchuri V Bourdelle KK Schwarzenbach W Bonnin O Nguyen BY Doris B Bœuf F Skotnicki T Faynot O Low leakage and low variability ultra-thin body and buried oxide (UT2B) SOI technology for 20 nm low power CMOS and beyond 2010 Symposium on VLSI Technology (VLSIT) 2010 57 58
  84. Tsuchiya R Horiuchi M Kimura S Yamaoka M Kawahara T Maegawa S Ipposhi T Ohji Y Matsuoka H Silicon on thin BOX: a new paradigm of the CMOSFET for low-power high-performance application featuring wide-range back-bias control IEEE International Electron Devices Meeting - IEDM 2004 631 634
  85. Kilchytska V Arshad MKMd Makovejev S Olsen SH Andrieu F Faynot O Raskin J-P Flandre D Ultra-thin body and BOX SOI analog figures of merit Sixth Workshop of the Thematic Network on Silicon on Insulator technology, devices and circuits - EuroSOI'11 2011 143 144
  86. Makovejev S Olsen SH Raskin J-P RF extraction of self-heating effects in FinFETs of various geometries 11 th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems - SiRF'11 2011 117 120
  87. O’Neill A., Agaiby R., Olsen S., Yang Y., Hellstrom P.-E., Ostling M., Oehme M., Lyutovich K., Kasper E., Eneman G., Verheyen P., Loo R., Claeys C., Fiegna C., Sangiorgi E., Reduced self-heating by strained silicon substrate engineering, 10.1016/j.apsusc.2008.02.172
  88. Fiegna Claudio, Yang Yang, Sangiorgi Enrico, O'Neill Anthony G., Analysis of Self-Heating Effects in Ultrathin-Body SOI MOSFETs by Device Simulation, 10.1109/ted.2007.911354
  89. Jomaah J., Ghibaudo G., Balestra F., Analysis and modeling of self-heating effects in thin-film SOI MOSFETs as a function of temperature, 10.1016/0038-1101(94)00130-8
  90. Su LT Goodson KE Antoniadis DA Flik MI Chung JE Measurement and modeling of self-heating effects in SOI nMOSFETs International Electron Devices Meeting - IEDM 1992 357 360
  91. Oshima K., Cristoloveanu S., Guillaumot B., Iwai H., Deleonibus S., Advanced SOI MOSFETs with buried alumina and ground plane: self-heating and short-channel effects, 10.1016/j.sse.2003.12.026
  92. Raleva Katerina, Vasileska Dragica, Goodnick Stephen M., Nedjalkov Mihail, Modeling Thermal Effects in Nanodevices, 10.1109/ted.2008.921263
  93. Vasileska Dragica, Raleva Katerina, Goodnick Stephen M., Self-Heating Effects in Nanoscale FD SOI Devices: The Role of the Substrate, Boundary Conditions at Various Interfaces, and the Dielectric Material Type for the BOX, 10.1109/ted.2009.2032615
  94. Liua, Electrochem Soc Trans, 34, 37 (2011)
  95. Liu Q Monsieur F Kumar A Yamamoto T Yagishita A Kulkarni P Ponoth S Loubet N Cheng K Khakifirooz A Haran B Vinet M Cai J Kuss J Linder B Grenouillet L Mehta S Khare P Berliner N Levin T Kanakasabapathy S Upham A Sreenivasan R Le Tiec Y Posseme N Li J Demarest J Smalley L Leobandung E Monfray S Boeuf V Skotnicki T Ishimaru K Takayanagi M Kleemeier W Bu H Luning S Hook T Khare M Shahidi G Doris B Sampson R Impact of back bias on ultra-thin body and BOX (UTBB) devices Symposium on VLSI Technology (VLSIT) 2011 160 161
  96. Tenbroek BM Redman-White W Uren MJ Lee MSL Ward MCL Identification of thermal and electrical time constants in SOI MOSFETs from small signal measurements Proc. of 23 rd European Solid-State Device Research Conference (ESSDERC) 1993 189 192
  97. Howes R., Redman-White W., A small-signal model for the frequency-dependent drain admittance in floating-substrate MOSFET's, 10.1109/4.148327
  98. Kilchytska V Levacq D Lederer D Raskin J-P Flandre D Substrate effect on the small-signal characteristic of SOI MOSFETs Proc. of 32 rd ESSDERC 2002 519 522
  99. Kilchytska Valeria, Pailloncy Guillaume, Lederer Dimitri, Raskin Jean-Pierre, Collaert Nadine, Jurczak Malgorzata, Flandre Denis, Frequency Variation of the Small-Signal Output Conductance of Decananometer MOSFETs Due to Substrate Crosstalk, 10.1109/led.2007.895374
  100. Kilchytska Valeria, Levacq David, Lederer Dimitri, Pailloncy Guillaume, Raskin Jean-Pierre, Flandre Denis, Substrate Effect on the Output Conductance Frequency Response of SOI MOSFETs, Nanoscaled Semiconductor-on-Insulator Structures and Devices ISBN:9781402063787 p.221-238, 10.1007/978-1-4020-6380-0_16
  101. Kilchytska V., Chung T.M., Olbrechts B., Vovk Ya., Raskin J.-P., Flandre D., Electrical characterization of true Silicon-On-Nothing MOSFETs fabricated by Si layer transfer over a pre-etched cavity, 10.1016/j.sse.2007.07.021
  102. Jurczak M., Skotnicki T., Paoli M., Tormen B., Martins J., Regolini J.L., Dutartre D., Ribot P., Lenoble D., Pantel R., Monfray S., Silicon-on-Nothing (SON)-an innovative process for advanced CMOS, 10.1109/16.877181
  103. Ernst T., Tinella C., Raynaud C., Cristoloveanu S., Fringing fields in sub-0.1 μm fully depleted SOI MOSFETs: optimization of the device architecture, 10.1016/s0038-1101(01)00111-3
  104. Makovejev S Raskin J-P Flandre D Andrieu F Olsen SH Kilchytska V Comparison of small-signal output conductance frequency dependence in UTBB SOI MOSFETs with and without ground plane IEEE International SOI Conference - SOI 2011 2011 263 264
  105. Frei J., Johns C., Vazquez A., Xiong W., Cleavelin C.R., Schulz T., Chaudhary N., Gebara G., Zaman J.R., Gostkowski M., Matthews K., Colinge J.-P., Body Effect in Tri- and Pi-Gate SOI MOSFETs, 10.1109/led.2004.839223
  106. Thompson S Anand N Armstrong M Auth C Arcot B Alavi M Bai P Bielefeld J Bigwood R Brandenburg J Buehler M Cea S Chikarmane V Choi C Frankovic R Ghani T Glass G Han W Hoffmann T Hussein M Jacob P Jain A Jan C Joshi S Kenyon C Klaus J Klopcic S Luce J Ma Z Mcintyre B Mistry K Murthy A Nguyen P Pearson H Sandford T Schweinfurth R Shaheed R Sivakumar S Taylor M Tufts B Wallace C Wang P Weber C Bohr M A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low-k ILD, and 1 µm 2 SRAM cell IEEE International Electron Devices Meeting (IEDM) 2002 61 64
  107. Shang H., Frank M. M., Gusev E. P., Chu J. O., Bedell S. W., Guarini K. W., Ieong M., Germanium channel MOSFETs: Opportunities and challenges, 10.1147/rd.504.0377
  108. Caymax M Eneman G Bellenger F Merckling C Delabie A Wang G Loo R Simoen E Mitard J De Jaeger B Hellings G De Meyer K Meuris M Heyns M Germanium for advanced CMOS anno 2009: a SWOT analysis IEEE International Electron Devices Meeting (IEDM) 2009 1 4
  109. Passlack M Zurcher P Rajagopalan K Droopad R Abrokwah J Tutt M Park Y-B Johnson E Hartin O Zlotnicka A Fejes P Hill RJW Moran DAJ Li X Zhou H Macintyre D Thoms S Asenov A Kalna K Thayne IG High mobility III-V MOSFETs for RF and digital applications IEEE International Electron Devices Meeting (IEDM) 2007 621 624
  110. Chen J., Comparison of TiSi[sub 2], CoSi[sub 2], and NiSi for Thin-Film Silicon-on-Insulator Applications, 10.1149/1.1837833
  111. Lee SH Shin DS Rhee HS Ueno T Park HLMH Lee N-I Kang H-K Suh K-P Highly controllable cyclic selective epitaxial growth (CySEG) for 65 nm CMOS technology and beyond IEEE International Electron Devices Meeting (IEDM) 2004 1051 1054
  112. Valentin RaphaËl, Dubois Emmanuel, Raskin Jean-Pierre, Larrieu Guilhem, Dambrine Gilles, Lim Tao Chuan, Breil Nicolas, Danneville FranÇois, RF Small-Signal Analysis of Schottky-Barrier p-MOSFET, 10.1109/ted.2008.919382
  113. Valentin R., Dubois E., Larrieu G., Raskin J.-P., Dambrine G., Breil N., Danneville F., Optimization of RF Performance of Metallic Source/Drain SOI MOSFETs Using Dopant Segregation at the Schottky Interface, 10.1109/led.2009.2031254
  114. Pearman Dominic J., Pailloncy Guillaume, Raskin Jean-Pierre, Larson John M., Snyder John P., Parker Evan H. C., Whall Terence E., Static and High-Frequency Behavior and Performance of Schottky-Barrier p-MOSFET Devices, 10.1109/ted.2007.904985
  115. Raskin J.-P., Pearman D.J., Pailloncy G., Larson J.M., Snyder J., Leadley D.L., Whall T.E., High-Frequency Performance of Schottky Source/Drain Silicon pMOS Devices, 10.1109/led.2008.918250
  116. Reckinger Nicolas, Bayot Vincent, Yarekha Dmitri A., Dubois Emmanuel, Godey Sylvie, Wallart Xavier, Larrieu Guilhem, Łaszcz Adam, Ratajczak Jacek, Jacques Pascal J., Raskin Jean-Pierre, Schottky barrier lowering with the formation of crystalline Er silicide on n-Si upon thermal annealing, 10.1063/1.3136849
  117. Reckinger Nicolas, Dubois Emmanuel, Larrieu Guilhem, Flandre Denis, Raskin Jean-Pierre, Afzalian Aryan, Low temperature tunneling current enhancement in silicide/Si Schottky contacts with nanoscale barrier width, 10.1063/1.3567546
  118. Reckinger Nicolas, Poleunis Claude, Dubois Emmanuel, Augustin Duţu Constantin, Delcorte Arnaud, Raskin Jean-Pierre, Very low effective Schottky barrier height for erbium disilicide contacts on n-Si through arsenic segregation, 10.1063/1.3608159
  119. Urban C., Emam M., Sandow C., Zhao Q.T., Fox A., Mantl S., Raskin J.-P., Small-signal analysis of high-performance p- and n-type SOI SB-MOSFETs with dopant segregation, 10.1016/j.sse.2010.04.013
  120. Urban Christoph, Emam Mostafa, Sandow Christian, Knoch Joachim, Qing-Tai Zhao, Raskin Jean-Pierre, Mantl Siegfried, Radio-Frequency Study of Dopant-Segregated n-Type SB-MOSFETs on Thin-Body SOI, 10.1109/led.2010.2045220
  121. Khakifirooz Ali, Cheng Kangguo, Reznicek Alexander, Adam Thomas, Loubet Nicolas, He Hong, Kuss James, Li Juntao, Kulkarni Pranita, Ponoth Shom, Sreenivasan Raghavasimhan, Liu Qing, Doris Bruce, Shahidi Ghavam, Scalability of Extremely Thin SOI (ETSOI) MOSFETs to Sub-20-nm Gate Length, 10.1109/led.2011.2174411
  122. Cheng K Khakifirooz A Kulkarni P Ponoth S Kuss J Edge LF Kimball A Kanakasabapathy S Schmitz S Reznicek A Adam T He H Mehta S Upham A Seo S-C Herman JL Johnson R Zhu Y Jamison P Haran BS Zhu Z Fan S Bu H Sadana DK Kozlowski P O'Neill J Dorins B Shahidi G Extremely thin SOI (ETSOI) technology: past, present, and future Proc. IEEE International SOI Conference 2010 1 4
  123. Ko C Kuan T Zhang K A novel CVD-SiBCN low-k spacer technology for high-speed applications Symposium on VLSI Technology 39 2008 3 4
  124. Niebojewski H Le Royer C Morand Y Jaud M Rozeau O Dubois E Poiroux T Extra-low parasitic gate-to-contacts capacitance architecture for sub-14 nm transistor nodes Ninth Workshop of the Thematic Network on Silicon on Insulator technology, devices and circuits - EuroSOI'13 2013 2 3
  125. Knickerbocker J. U., Andry P. S., Dang B., Horton R. R., Interrante M. J., Patel C. S., Polastre R. J., Sakuma K., Sirdeshmukh R., Sprogis E. J., Sri-Jayantha S. M., Stephens A. M., Topol A. W., Tsang C. K., Webb B. C., Wright S. L., Three-dimensional silicon integration, 10.1147/jrd.2008.5388564
  126. Marchal P Van der Plas G Eneman G Moroz V Badaroglu M Mercha A Thijs S Linten D Guruprasad K Stucchi M Vandevelde B O'Prins H Cherman V Croes K Redolfi A La Manna A Travaly Y Beyne E Cartuyvels R 3D technology roadmap and status 2011 IEEE International Interconnect Technology Conference and 2011 Materials for Advanced Metallization (IITC/MAM) 2011 1 3
  127. Lederer D., Raskin Jean-Pierre, Effective resistivity of fully-processed SOI substrates, 10.1016/j.sse.2004.12.003
  128. Lederer D., Raskin J.-P., New substrate passivation method dedicated to HR SOI wafer fabrication with increased substrate resistivity, 10.1109/led.2005.857730
  129. Lederer Dimitri, Raskin Jean-Pierre, RF Performance of a Commercial SOI Technology Transferred Onto a Passivated HR Silicon Substrate, 10.1109/ted.2008.923564
  130. Roda Neve C., Raskin J-P, RF Harmonic Distortion of CPW Lines on HR-Si and Trap-Rich HR-Si Substrates, 10.1109/ted.2012.2183598
  131. Ben Ali K., Roda Neve C., Gharsallah A., Raskin J.-P, Ultrawide Frequency Range Crosstalk Into Standard and Trap-Rich High Resistivity Silicon Substrates, 10.1109/ted.2011.2170074
Bibliographic reference Raskin, Jean-Pierre. Silicon-on-insulator MOSFETs models in analog/RF domain. In: International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, Vol. 27, no. 5-6, p. 707-735 (2014)
Permanent URL http://hdl.handle.net/2078.1/160273