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Study of Back Biasing Schemes for ULV Logic from the Gate Level to the IP Level

Bibliographic reference de Streel, Guerric ; Bol, David. Study of Back Biasing Schemes for ULV Logic from the Gate Level to the IP Level. In: Journal of Low Power Electronics and Applications, Vol. 4, no.3, p. 168-187 (07/07/2014)
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  1. Bol David, De Vos Julien, Hocquet Cédric, Botman François, Durvaux François, Boyd Sarah, Flandre Denis, Legat Jean-Didier, SleepWalker: A 25-MHz 0.4-V Sub- $\hbox{mm}^{2}$ 7- $\mu\hbox{W/MHz}$ Microcontroller in 65-nm LP/GP CMOS for Low-Carbon Wireless Sensor Nodes, 10.1109/jssc.2012.2218067
  2. Bol David, Robust and Energy-Efficient Ultra-Low-Voltage Circuit Design under Timing Constraints in 65/45 nm CMOS, 10.3390/jlpea1010001
  3. Alioto M., Ultra-Low Power VLSI Circuit Design Demystified and Explained: A Tutorial, 10.1109/tcsi.2011.2177004
  4. Bol David, Flandre Denis, Legat Jean-Didier, Nanometer MOSFET Effects on the Minimum-Energy Point of Sub-45nm Subthreshold Logic---Mitigation at Technology and Circuit Levels, 10.1145/1870109.1870111
  5. Hwang Myeong-Eun, Roy Kaushik, ABRM: Adaptive $ \beta$-Ratio Modulation for Process-Tolerant Ultradynamic Voltage Scaling, 10.1109/tvlsi.2008.2010767
  6. Calhoun B.H., Wang A., Chandrakasan A., Modeling and sizing for minimum energy operation in subthreshold circuits, 10.1109/jssc.2005.852162
  7. Bol D., Ambroise R., Flandre D., Legat J.-D., Interests and Limitations of Technology Scaling for Subthreshold Logic, 10.1109/tvlsi.2008.2005413
  8. Ono G., Miyazaki M., Threshold-voltage balance for minimum supply operation, 10.1109/jssc.2003.810043