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Study of Back Biasing Schemes for ULV Logic from the Gate Level to the IP Level

Bibliographic reference de Streel, Guerric ; Bol, David. Study of Back Biasing Schemes for ULV Logic from the Gate Level to the IP Level. In: Journal of Low Power Electronics and Applications, Vol. 4, no.3, p. 168-187 (07/07/2014)
Permanent URL http://hdl.handle.net/2078.1/154424
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