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Impact of Back Gate Biasing Schemes on Energy and Robustness of ULV Logic in 28nm UTBB FDSOI Technology

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de Streel, Guerric [UCL] Bol, David [UCL]

Minimum energy per operation is typically achieved in the subthreshold region where low speed and low robustness are two challenging problems. This paper studies the impact of Back Biasing (BB) schemes on these features for FDSOI technology. We show that Forward BB can help cover a wider design space in term of optimal frequency of operation while keeping minimum energy. Asymmetric BB between NMOS and PMOS can mitigate the effect of systematic mismatch on Minimum Energy Point (MEP) and robustness. With optimal asymmetric BB, we achieve either a MEP reduction up to 18% or a 36 speedup at the MEP.

Document type Communication à un colloque (Conference Paper) – Présentation orale avec comité de sélection
Access type Accès restreint
Publication date 2013
Language Anglais
Conference "2013 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED 2013)", Beijing (P.R.China) (du 04/09/2013 au 06/09/2013)
Peer reviewed yes
Host document
Publication status Publié
Affiliation UCL - SST/ICTM/ELEN - Pôle en ingénierie électrique
Keywords CMOS FDSOI ; 28nm ; Subthreshold logic ; Ultra-low power ; Ultra-low-voltage ; Back gate biasing ; Robustness ; Die yield
Links
Bibliographic reference de Streel, Guerric ; Bol, David. Impact of Back Gate Biasing Schemes on Energy and Robustness of ULV Logic in 28nm UTBB FDSOI Technology.2013 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED 2013) (Beijing (P.R.China), du 04/09/2013 au 06/09/2013).
Permanent URL http://hdl.handle.net/2078.1/152743