The charge coupling between the gate and substrate is a fundamental property of any fully-depleted silicon-on-insulator (SOI) MOS transistor, which manifests itself as a dependence of electrical characteristics at one Si film/dielectric interface on charges at the opposite interface and opposite gate bias. Traditionally, gate-to-substrate coupling in SOI MOS transistors is described by the classical Lim-Fossum model. However, in the case of SOI MOS transistors with ultra-thin silicon bodies, significant deviations from this model are observed. In this paper, the behavior of gate coupling in SOI MOS structures with ultra-thin silicon films and ultra-thin gate dielectrics is studied and analyzed using experimental data and one-dimensional numerical simulations in classical and quantum-mechanical modes. It is shown that in these advanced transistor structures, coupling characteristics (dependences of the front- and back-gate threshold voltages on the opposite gate bias) feature a larger slope and much wider (more than doubled) linear region than that predicted by the Lim-Fossum model. These differences originate from both electrostatic and quantization effects. A simple analytical model taking into account these effects and being in good agreement with numerical simulations and experimental results is proposed.
