de Streel, Guerric
[UCL]
De Vos, Julien
[UCL]
Flandre, Denis
[UCL]
Bol, David
[UCL]
A linear regulator for point of load power delivery with 280nA quiescent current and 0:008mm2 area is presented in this paper. Strong specifications on Power Supply Rejection Ratio (PSRR) and power consumption were included in the design at 0:5V output voltage to supply both low power analog and Ultra-Low-Voltage (ULV) digital circuits with a maximum load current of 0:5mA. Current mode pole splitting and NMOS source follower power stage allows us to optimize PSRR and guarantee stability whilst keeping low silicon footprint for the 6pf on-chip capacitor. We demonstrate its use for supplying a ULV CMOS imager that was manufactured in 65nm LP/GP CMOS process.
Bibliographic reference |
de Streel, Guerric ; De Vos, Julien ; Flandre, Denis ; Bol, David. A 65nm 1V to 0.5V Linear Regulator with Ultra Low Quiescent Current for Mixed-Signal ULV SoCs.2014 IEEE FTFC Conference (Monaco, du 04/05/2014 au 06/05/2014). |
Permanent URL |
http://hdl.handle.net/2078.1/145581 |