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Gate leakage currents model for FinFETs implemented in Verilog-A for electronic circuits design

Bibliographic reference Garduno, Salvador I. ; Alvarado Pulido, José Joaquin ; Cerdeira, Antonio ; Estrada, Magali ; Kilchytska, Valeriya ; et. al. Gate leakage currents model for FinFETs implemented in Verilog-A for electronic circuits design. In: International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, p. 15 (2014)
Permanent URL http://hdl.handle.net/2078.1/141233
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