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Improved synthesis of gain-boosted regulated-cascode CMOS stages using symbolic analysis and gm/ID methodology

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Flandre, Denis [UCL] Viviani, A. [UCL] Eggermont, Jean-Pierre [UCL] Gentinne, B. [UCL] Jespers, Paul [UCL]

A systematic study of the gain-boosted regulated-cascode operational transconductance amplifier (OTA) CMOS stage is presented. Symbolic analysis is used first to describe the pole-zero behaviour and second to propose design criteria for optimal settling time. A synthesis procedure based on the “gm/ID” methodology is considered further on for quick optimization of the architecture based on the dc open-loop gain, transition frequency, and settling time specifications. Practical design cases are finally discussed.

Document type Article de périodique (Journal article) – Article de recherche
Publication date 1997
Language Anglais
Journal information "IEEE Journal of Solid State Circuits" - Vol. 32, no.7, p. 1006-1012 (07/1997)
Peer reviewed yes
Publisher I E E E
issn 0018-9200
e-issn 1558-173X
Publication status Publié
Affiliation UCL - FSA/ELEC - Département d'électricité
Keywords CMOS analog ; Transconductance ; Transient response ; integrated circuits ; Circuit stability ; Circuit synthesis ; Design optimization ; Frequency synthesizers ; Integrated circuit synthesis ; Operational amplifiers ; Optimization methods
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Bibliographic reference Flandre, Denis ; Viviani, A. ; Eggermont, Jean-Pierre ; Gentinne, B. ; Jespers, Paul. Improved synthesis of gain-boosted regulated-cascode CMOS stages using symbolic analysis and gm/ID methodology. In: IEEE Journal of Solid State Circuits, Vol. 32, no.7, p. 1006-1012 (07/1997)
Permanent URL http://hdl.handle.net/2078.1/134315