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Improved modeling of gate leakage currents for fin-shaped field-effect transistors

Bibliographic reference Garduῆo, S.I. ; Cerdeira, Antonio ; Estrada, Magali ; Alvarado Pulido, José Joaquin ; Kilchytska, Valeriya ; et. al. Improved modeling of gate leakage currents for fin-shaped field-effect transistors. In: Journal of Applied Physics, Vol. 113, no.124507, p. 124507/1-9 (28/03/2013)
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  1. International Technology Roadmap Semiconductors (ITRS), Process Integration, Devices and Structures (2009)
  2. FinFETs and Other Multi-Gate Transistors, ISBN:9780387717517, 10.1007/978-0-387-71752-4
  3. Engström O., Will the Insulated Gate Transistor Concept Survive Next Decade? Future Trends in Microelectronics: Up the Nano Creek (2007)
  4. Iwai Hiroshi, Ohmi Shun'ichiro, Silicon integrated circuit technology from past to future, 10.1016/s0026-2714(02)00032-x
  5. Kauerauf Thomas, Govoreanu Bogdan, Degraeve Robin, Groeseneken Guido, Maes Herman, Scaling CMOS: Finding the gate stack with the lowest leakage current, 10.1016/j.sse.2005.01.018
  6. Cheng B., Cao M., Rao R., Inani A., Vande Voorde P., Greene W.M., Stork J.M.C., Zhiping Yu, Zeitzoff P.M., Woo J.C.S., The impact of high-κ gate dielectrics and metal gate electrodes on sub-100 nm MOSFETs, 10.1109/16.772508
  7. Yee-Chia Yeo, Tsu-Jae King, Chenming Hu, MOSFET gate leakage modeling and selection guide for alternative gate dielectrics based on leakage considerations, 10.1109/ted.2003.812504
  8. Darbandy Ghader, Ritzenthaler Romain, Lime Francois, Garduño Ivan, Estrada Magali, Cerdeira Antonio, Iñiguez Benjamin, Analytical modeling of the gate tunneling leakage for the determination of adequate high-k dielectrics in double-gate SOI MOSFETs at the 22nm node, 10.1016/j.sse.2010.06.015
  9. T. Hoffmann, G. Doornbos, I. Ferain, N. Collaert, P. Ziemmerman, M. Goodwin, R. Rooyackers, A. Kottantharayil, Y. Yim, A. Dixit, K. De Meyer, M. Jurczak, and S. Biesemans, in IEEE IEDM Technical Digest (Washington, DC, 2005), pp. 725–728.
  10. Tsormpatzoglou A., Dimitriadis C.A., Mouis M., Ghibaudo G., Collaert N., Experimental characterization of the subthreshold leakage current in triple-gate FinFETs, 10.1016/j.sse.2009.01.008
  11. Choi Yang-Kyu, Ha Daewon, King Tsu-Jae, Bokor Jeffrey, Investigation of Gate-Induced Drain Leakage (GIDL) Current in Thin Body Devices: Single-Gate Ultra-Thin Body, Symmetrical Double-Gate, and Asymmetrical Double-Gate MOSFETs, 10.1143/jjap.42.2073
  12. Yuan Xiaobin, Park Jae-Eun, Wang Jing, Zhao Enhai, Ahlgren David C., Hook Terence, Yuan Jun, Chan Victor W. C., Shang Huiling, Liang Chu-Hsin, Lindsay Richard, Park Sungjoon, Choo Hyotae, Gate-Induced-Drain-Leakage Current in 45-nm CMOS Technology, 10.1109/tdmr.2008.2002350
  13. Garduño S. I., Cerdeira A., Estrada M., Alvarado J., Kilchytska V., Flandre D., Contribution of carrier tunneling and gate induced drain leakage effects to the gate and drain currents of fin–shaped field–effect transistors, 10.1063/1.3575324
  14. Cerdeira A., Moldovan O., Iñiguez B., Estrada M., Modeling of potentials and threshold voltage for symmetric doped double-gate MOSFETs, 10.1016/j.sse.2007.10.046
  15. Cerdeira Antonio, Iñiguez Benjamín, Estrada Magali, Compact model for short channel symmetric doped double-gate MOSFETs, 10.1016/j.sse.2008.03.009
  16. Rudenko T., Kilchytska V., Collaert N., Jurczak M., Nazarov A., Flandre D., Reduction of gate-to-channel tunneling current in FinFET structures, 10.1016/j.sse.2007.09.016
  17. Schuegraf K.F., Chenming Hu, Hole injection SiO/sub 2/ breakdown model for very low voltage lifetime extrapolation, 10.1109/16.285029
  18. W.C. Lee and C. Hu, in 2000 International Symposium on VLSI Technology (Honolulu, Hawai, 2000), pp. 198–199.
  19. Lee Q., Martin S.C., Mensa D., Smith R.P., Guthrie J., Rodwell M.J.W., Submicron transferred-substrate heterojunction bipolar transistors, 10.1109/55.778155
  20. Wen-Chin Lee, Chenming Hu, Modeling CMOS tunneling currents through ultrathin gate oxide due to conduction- and valence-band electron and hole tunneling, 10.1109/16.930653
  21. Moldovan Oana, Cerdeira Antonio, Jiménez David, Raskin Jean-Pierre, Kilchytska Valeria, Flandre Denis, Collaert Nadine, Iñiguez Benjamin, Compact model for highly-doped double-gate SOI MOSFETs targeting baseband analog applications, 10.1016/j.sse.2007.02.039
  22. Gurfinkel Moshe, Suehle John S., Shapira Yoram, Enhanced gate induced drain leakage current in HfO2 MOSFETs, 10.1016/j.mee.2009.02.029
  23. Fleischer S., Lai P. T., Cheng Y. C., Simplified closed‐form trap‐assisted tunneling model applied to nitrided oxide dielectric capacitors, 10.1063/1.351923
  24. Fleischer S., Lai P. T., Cheng Y. C., A new method for extracting the trap energy in insulators, 10.1063/1.352934
  25. J. Ramos, E. Augendre, A. Kottantharayil, A. Mercha, E. Simoen, M. Rosmeulen, S. Severi, C. Kerner, T. Chiarella, A. Nackaerts, I. Ferain, T. Hoffmann, M. Jurczak, and S. Biesemans, in 8th International Conference on Solid-State and Integrated Circuit Technology (Shangai, China, 2006), pp. 72–74.
  26. Kilchytska V., Alvarado J., Collaert N., Rooyackers R., Put S., Simoen E., Claeys C., Flandre D., Gate-edge charges related effects and performance degradation in advanced multiple-gate MOSFETs, 10.1016/j.sse.2011.01.008
  27. Dixit A., Kottantharayil A., Collaert N., Goodwin M., Jurczak M., DeMeyer K., DeMeyer K., Analysis of the Parasitic S/D Resistance in Multiple-Gate FETs, 10.1109/ted.2005.848098
  28. K. Henson, N. Collaert, M. Demand, M. Goodwin, S. Brus, R. Rooyackers, A. van Ammel, B. Degroote, M. Ercken, C. Baerts, K. G. Anil, A. Dixit, S. Beckx, T. Schram, W. Deweerd, W. Boullart, M. Schaekers, S. De Gendt, K. De Meyer, Y. Yim, J. C. Hooker, M. Jurczak, and S. Biesemans, in 2005 VLSI-TSA Technology Symposium (Hsinshu, Taiwan, 2005), pp. 136–137.
  29. Robertson J., Band structures and band offsets of high K dielectrics on Si, 10.1016/s0169-4332(01)00832-7
  30. Wilk G. D., Wallace R. M., Electrical properties of hafnium silicate gate dielectrics deposited directly on silicon, 10.1063/1.124036
  31. Kapila G., Kaczer B., Nackaerts A., Collaert N., Groeseneken G. V., Direct Measurement of Top and Sidewall Interface Trap Density in SOI FinFETs, 10.1109/led.2007.891263
  32. Sugiura S., Degradation in Quality of Very Thin Gate Oxide by Arsenic Ion Implantation, 10.1149/1.2100531