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A Fast ULV Logic Synthesis Flow in Many-Vt CMOS Processes for Minimum Energy Under Timing Constraints

Bibliographic reference Bol, David ; Hocquet, Cédric ; Regazzoni, Francesco. A Fast ULV Logic Synthesis Flow in Many-Vt CMOS Processes for Minimum Energy Under Timing Constraints. In: IEEE Transactions on Circuits and Systems. Part 2: Express Briefs, Vol. 59, no. 12, p. 947-951 (2012)
Permanent URL http://hdl.handle.net/2078.1/125016