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Multi-VT ultra-low-power FPGA implementation in 65nm CMOS technology

Bibliographic reference de Streel, Guerric ; Bol, David ; Legat, Jean-Didier. Multi-VT ultra-low-power FPGA implementation in 65nm CMOS technology.Faible Tension Faible Consommation (FTFC), 2012 IEEE (Paris (France), du 06/06/2012 au 08/06/2012). In: Faible Tension Faible Consommation (FTFC), 2012 IEEE, 2012, p. 4 pages
Permanent URL http://hdl.handle.net/2078.1/124567