Substrate loss mechanisms for microstrip and CPW transmission lines on lossy silicon wafers

Loss mechanisms for microstrip and coplanar transmission lines on lossy silicon substrates are analyzed. It is shown that depending on the quality of the silicon/oxide interface the losses can be strongly influenced by the applied bias. It is also proven that MS losses are much less sensitive to the line DC condition than CPW lines. This is supported both by experimental results and numerical simulations. A continuous analysis of the losses is performed from accumulation to strong inversion and we attribute the observed effects to changes in the carrier static distribution underneath the oxide. It is concluded that neglecting the variations of RF losses vs DC bias conditions can lead to important inaccuracies on the extracted values of circuit and device physical parameters.