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Problems in designing thin-film accumulation-mode p-channel SOI MOSFET's for CMOS digital circuit environment

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Flandre, Denis [UCL]

A back-accumulation conduction mechanism ignored in previously-published analyses is shown to be the prime factor in the definition of the threshold voltage of the thin-film accumulation-mode p-channel SOI MOSFET when the device is integrated in a typical digital circuit environment. A new formulation which overcomes this problem is presented, then used to discuss problems of a tradeoff between film doping and threshold voltage as a function of other technological parameters.

Document type Article de périodique (Journal article) – Article de recherche
Publication date 1991
Language Anglais
Journal information "Electronics Letters" - Vol. 27, no. 14, p. 1280-1282 (July 4 (July 4, 1991)
Peer reviewed yes
Publisher The Institution of Engineering and Technology (United Kingdom)
issn 0013-5194
e-issn 1350-911X
Publication status Publié
Affiliation UCL - FSA/ELEC - Département d'électricité
Keywords CMOS integrated circuits ; Digital integrated circuits ; Insulated gate field effect transistors ; Semiconductor device models ; Thin film transistors
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Bibliographic reference Flandre, Denis. Problems in designing thin-film accumulation-mode p-channel SOI MOSFET's for CMOS digital circuit environment. In: Electronics Letters, Vol. 27, no. 14, p. 1280-1282 (July 4 (July 4, 1991)
Permanent URL http://hdl.handle.net/2078.1/111572