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Word-parallel CRC computation on VLIW DSP

Onglets principaux

Hubaux, D Legat, Jean-Didier [UCL]

Cyclic redundancy check (CRC) is widely used for error detection. For optimal performances a method has been developed for bit-parallel processing, but it may not take advantage of parallel processor architecture. Here, a method is proposed for using. the toll power of a very long instruction word (VLIW) digital signal processor (DSP) architecture in CRC computation. The method to at least four times faster for 8, 16 and 32 bits CRC.

Type de document Article de périodique (Journal article) – Article de recherche
Année de publication 2002
Langue Anglais
Information sur le périodique "Electronics Letters" - Vol. 38, no. 2, p. 64-65 (2002)
Peer reviewed oui
Editeur Iee-inst Elec Eng (Hertford)
issn 0013-5194
e-issn 1350-911X
Statut de la publication Publié
Affiliations UCL - FSA/ELEC - Département d'électricité
Liens
Référence bibliographique Hubaux, D ; Legat, Jean-Didier. Word-parallel CRC computation on VLIW DSP. In: Electronics Letters, Vol. 38, no. 2, p. 64-65 (2002)
Permalien http://hdl.handle.net/2078.1/42172