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Displaying 9 results.
    • Journal article
    SleepRunner: A 28-nm FDSOI ULP Cortex-M0 MCU With ULL SRAM and UFBR PVT Compensation for 2.6–3.6-μW/DMIPS 40–80-MHz Active Mode and 131-nW/kB Fully Retentive Deep-Sleep Mode
    Bol, David[UCL] Schramme, Maxime[UCL] Moreau, Ludovic[UCL] Xu, Pengcheng[UCL] Dekimpe, Rémi[UCL] Saeidi, Roghayeh[UCL] Haine, Thomas Frenkel, Charlotte[UCL] Flandre, Denis[UCL] (2021) IEEE Journal of Solid State Circuits — Vol. 56, no.7, p. 2256-2269 (2021)
    • Speech
    CAMEL: An Ultra-Low-Power VGA CMOS Imager based on a Time-Based DPS Array
    Haine, Thomas[UCL] Stas, François[UCL] de Streel, Guerric[UCL] Gimeno Gasca, Cecilia[UCL] Flandre, Denis[UCL] Bol, David[UCL] (2016) 10th International Conference on Distributed Smart Camera (ICDSC '16) — Paris (France)
    • Speech
    An 80-MHz 0.4V ULV SRAM macro in 28nm FDSOI achieving 28-fJ/bit access energy with a ULP bitcell and on-chip adaptive back bias generation
    Haine, Thomas[UCL] Nguyen, Quoc-Khoi[UCL] Stas, François[UCL] Moreau, Ludovic[UCL] Flandre, Denis[UCL] Bol, David[UCL] (2017) 43rd IEEE European Solid State Circuits Conference (ESSCIRC 2017) — Leuven (Belgium)
    • Speech
    Optimization of the area/robustness/speed trade-off in a 28nm FDSOI latch based on ULP diodes
    Haine, Thomas[UCL] Stas, François[UCL] Bol, David[UCL] (2014) 2014 IEEE FTFC Conference — Monaco
    • Speech
    Analysis and Optimization for Dynamic Read Stability in 28nm SRAM Bitcells
    Taha Elthakeb Naguib Youssef, Ahmed[UCL] Haine, Thomas[UCL] Flandre, Denis[UCL] Ismail, Yehea Elhamid, Hamdy Abd Bol, David[UCL] (2015) IEEE International Conference on Circuits and Systems (ISCAS 2015) — Lisbon (Portugal)
    • Dissertation
    Large array-based circuits in ULV SoCs : design and statistical assessment of SRAMs and CMOS imagers
    Haine, Thomas[UCL] (2018)
    • Speech
    Gradient Importance Sampling: an Efficient Statistical Extraction methodology of High-Sigma SRAM Dynamic Characteristics
    Haine, Thomas[UCL] Segers, Johan[UCL] Flandre, Denis[UCL] Bol, David[UCL] (2018) DATE 2018, Design, Automation and Test in Europe — Dresden (Germany)
    • Speech
    A 40-to-80MHz Sub-4µW/MHz ULV Cortex-M0 MCU SoC in 28nm FDSOI with Dual-Loop Adaptive Back-Bias Generator for 20µs Wake-Up From Deep Fully Retentive Sleep Mode
    Bol, David[UCL] Schramme, Maxime[UCL] Moreau, Ludovic[UCL] Haine, Thomas[UCL] Xu, Pengcheng[UCL] Frenkel, Charlotte[UCL] Dekimpe, Rémi[UCL] Stas, François Flandre, Denis[UCL] (2019) 2019 IEEE International Solid- State Circuits Conference - (ISSCC) — San Francisco (USA)
    • Speech
    An 8-T ULV SRAM macro in 28nm FDSOI with 7.4 pW/bit retention power and back-biased-scalable speed/energy trade-off
    Haine, Thomas[UCL] Flandre, Denis[UCL] Bol, David[UCL] (2018) IEEE S3S Conference — San Francisco (USA)