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1. • Journal article

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   Dynamic differential self-timed logic families for robust and low-power security ICs

   Hassoune, Ilham[UCL] Macé, François[UCL] Flandre, Denis[UCL] Legat, Jean-Didier[UCL] (2007) Integration : the V L S I journal — Vol. 40, no. 3, p. 355-364 (2007)
2. • Journal article

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   Building ultra-low-power high-temperature digital circuits in standard high-performance SOI technology

   Bol, David[UCL] De Vos, Julien[UCL] Ambroise, Renaud[UCL] Flandre, Denis[UCL] Legat, Jean-Didier[UCL] (2008) Solid-State Electronics — Vol. 52, no. 12, p. 1939-1945 (2008)
3. • Journal article

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   Low-swing current mode logic (LSCML): A new logic style for secure and robust smart cards against power analysis attacks

   Hassoune, Ilham[UCL] Macé, François[UCL] Flandre, Denis[UCL] Legat, Jean-Didier[UCL] (2006) Microelectronics — Vol. 37, no. 9, p. 997-1006 (2006)
4. • Journal article

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   ULPFA: A New Efficient Design of a Power-Aware Full Adder

   Hassoune, Ilham[UCL] Flandre, Denis[UCL] O'Connor, Ian Legat, Jean-Didier[UCL] (2010) IEEE Transactions on Circuits and Systems Part 1: Regular Papers — Vol. 57, no. 8, p. 2066-2074 (2010)
5. • Journal article

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   Interests and Limitations of Technology Scaling for Subthreshold Logic

   Bol, David[UCL] Ambroise, Renaud[UCL] Flandre, Denis[UCL] Legat, Jean-Didier[UCL] (2009) IEEE Transactions on Very Large Scale Integration (VLSI) Systems — Vol. 17, no. 10, p. 1508-1519 (2009)
6. • Journal article

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   A new multi-valued current-mode adder based on negative-differential resistance using ULP diodes

   Hassoune, H Flandre, Denis[UCL] Legat, Jean-Didier[UCL] Drummond, A Gaudissart, Anne[UCL] Bol, David[UCL] Levacq, D. (2005) Solid-State Electronics — Vol. 49, no. 7, p. 1185-1191 (2005)
7. • Speech

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   Branch-Based Design of Carry Calculation Cell for Ultra-Low Power and High-Temperature Applications

   Hassoune, Ilham[UCL] Nève, Amaury Legat, Jean-Didier[UCL] Flandre, Denis[UCL] (2004) International High Temperature Electronics Conference and Exhibition (HITECH 2004) — Santa Fe (New Mexico, USA)
8. • Speech

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   Hybrid full-adder cell in 0.13 µm PD SOI CMOS for low-voltage low-power applications

   Hassoune, Ilham[UCL] Legat, Jean-Didier[UCL] Flandre, Denis[UCL] (2005) EUROSOI 2005 - First Workshop of the Thematic Network on Silicon on Insulator technology, devices and circuits — Granada, Spain
9. • Speech

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   Bulk vs SOI CMOS APS optimal design for low power low voltage applications

   Afzalian, Aryan[UCL] Delatte, Pierre[UCL] Legat, Jean-Didier[UCL] Flandre, Denis[UCL] (2001) ECCTD'01 - European Conference on Circuit Theory and Design — Espoo (Finland)
10. • Speech

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    Oscillateurs en Anneau CMOS SOI à Basse Tension d'Alimentation.

    Flandre, Denis[UCL] Legat, Jean-Didier[UCL] Delatte, Pierre[UCL] (1999) 2èmes journées francophones d'études faible consommation FTFC'99 — Paris (France)
11. • Speech

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    PLL Jitter Behavioral Modeling and Simulation using HDL-A.

    Flandre, Denis[UCL] Legat, Jean-Didier[UCL] Delatte, Pierre[UCL] (1999) BMAS'99 — Orlando (USA)
12. • Speech

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    A Hybrid Full-adder Cell for High-Performance and Low-Power Design

    Hassoune, Ilham[UCL] Levacq, David[UCL] Drummond, Alexander[UCL] Gaudissart, Arnaud[UCL] Legat, Jean-Didier[UCL] Flandre, Denis[UCL] (2004) 11th Electronic Devices and Systems Conference 2004 (EDS'04) — Brno (Czech Republic)
13. • Speech

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    The ATHIS project: Advanced Techniques for High-Temperature System-on-Chip

    Flandre, Denis[UCL] Cabruja, L. Demeûs, Laurent[UCL] Dessard, Vincent[UCL] Jorda, X. Manzone, A. Richter, S. Russell, G. Legat, Jean-Didier[UCL] (2005) International Conference on High Temperature Electronics, HITEN, Paris, France, — Paris (France)
14. • Speech

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    Hybrid full-adder cell in 0.13 µm PD SOI CMOS for low-voltage low-power applications

    Hassoune, Ilham[UCL] Legat, Jean-Didier[UCL] Flandre, Denis[UCL] (2005) EUROSOI 2005 - First Workshop of the Thematic Network on Silicon on Insulator technology, devices and circuits — Granada, Spain
15. • Speech

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    Sub-45 nm fully-depleted SOI CMOS subthreshold logic for ultra-low-power applications

    Bol, David[UCL] Legat, Jean-Didier[UCL] Ambroise, Renaud[UCL] Flandre, Denis[UCL] (2008) 2008 IEEE International SOI Conference — New Paltz, NY, USA
16. • Speech

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    Impact of technology scaling on digital subthreshold circuits

    Bol, David[UCL] Legat, Jean-Didier[UCL] Ambroise, Renaud[UCL] Flandre, Denis[UCL] (2008) 2008 IEEE Computer Society Annual Symposium on VLSI — Montpellier, France
17. • Speech

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    Building ultra-low-power low-frequency digital circuits with high-speed devices

    Bol, David[UCL] Legat, Jean-Didier[UCL] Ambroise, Renaud[UCL] Flandre, Denis[UCL] (2007) 2007 14th IEEE International Conference on Electronics, Circuits and Systems (ICECS '07) — Marrakech, Morocco
18. • Speech

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    Ultra-low-power high-noise-margin logic with undoped FD SOI devices

    Bol, David[UCL] Legat, Jean-Didier[UCL] De Vos, Julien[UCL] Flandre, Denis[UCL] (2009) 2009 IEEE International SOI Conference — Foster City, CA, USA
19. • Speech

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    Comparison of Bulk vs SOI for low power low voltage CMOS imager

    Afzalian, Aryan[UCL] Delatte, Pierre[UCL] Legat, Jean-Didier[UCL] Flandre, Denis[UCL] (2001) 2001 IEEE International SOI Conference — Durango (Colorado/USA)
20. • Journal article

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    Nanometer MOSFET Effects on the Minimum-Energy Point of Sub-45nm Subthreshold Logic-Mitigation at Technology and Circuit Levels

    Bol, David[UCL] Flandre, Denis[UCL] Legat, Jean-Didier[UCL] (2010) ACM Transactions on Design Automation of Electronic Systems — Vol. 16, no. 1, p. 26 pages (2010)
21. • Speech

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    Design techniques for reliable timing closure in ULV SoCs

    Bol, David[UCL] Hocquet, Cédric[UCL] De Vos, Julien[UCL] Durvaux, François[UCL] Botman, François[UCL] Flandre, Denis[UCL] Legat, Jean-Didier[UCL] (2011) 2011 Subthreshold Microelectronics Conference — Lexington (MA)
22. • Speech

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    Investigation of low-power low-voltage circuit techniques for a hybrid full-adder cell

    Hassoune, Ilham[UCL] Legat, Jean-Didier[UCL] Neve, A. Flandre, Denis[UCL] (2004) 14th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS 2004) — Santorini (Greece)
23. • Speech

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    Robustness-aware sleep transistor engineering for power-gated nanometer subthreshold circuits

    Bol, David[UCL] Legat, Jean-Didier[UCL] Hocquet, Cédric[UCL] Flandre, Denis[UCL] (2010) 2010 IEEE International Symposium on Circuits and Systems. ISCAS 2010 — Paris, France
24. • Speech

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    A 25MHz 7μW/MHz Ultra-Low-Voltage Microcontroller SoC in 65nm LP/GP CMOS for Low-Carbon Wireless Sensor Nodes

    Bol, David[UCL] De Vos, Julien[UCL] Hocquet, Cédric[UCL] Durvaux, François[UCL] Botman, François[UCL] Boyd, Sarah Flandre, Denis[UCL] Legat, Jean-Didier[UCL] (2012) International Solid-State Circuits Conference — San Francisco
25. • Journal article

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    Efficient Multiple-Valued Signed-Digit Full Adder Based on NDR MOS Structures and its Application to an N-bit Current-Mode Constant-Time Adder

    Bol, David[UCL] Hassoune, Ilham[UCL] Levacq, David[UCL] Flandre, Denis[UCL] Legat, Jean-Didier[UCL] (2007) Journal of Multiple-Valued Logic and Soft Computing — Vol. 13, no. 1-2, p. 61-77 (2007)

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