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A circuit level 65nm node bulkand SOI technologies comparison for analog amplifiers

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Pollissard, Guillaume [UCL] Flandre, Denis [UCL]

This work aims at demonstrating the effectiveness of advanced SOI CMOS technologies from an analog circuit designer point of view. After a quick review of the compared analog figures of merit of bulk SOI technologies of the same 65nm node, we will present an automated sizing tool developed to target given specifications and deduce the remaining degrees of freedom. With this tool, we can fairly compare the SOI and bulk designs of a test amplifier.

Document type Communication à un colloque (Conference Paper) – Présentation orale avec comité de sélection
Publication date 2011
Language Anglais
Conference "Seventh Workshop of the Thematic Network on Silicon on Insulator technology, devices and circuits (EUROSOI 2011)", Granada (Espagne) (du 17/01/2011 au 19/01/2011)
Peer reviewed yes
Host document "Proceedings of the Seventh Workshop of the Thematic Network on Silicon on Insulator technology, devices and circuits (EUROSOI 2011)"
Affiliation UCL - SST/ICTM/ELEN - Pôle en ingénierie électrique
Keywords SOI ; analog amplifiers
Links
Bibliographic reference Pollissard, Guillaume ; Flandre, Denis. A circuit level 65nm node bulkand SOI technologies comparison for analog amplifiers.Seventh Workshop of the Thematic Network on Silicon on Insulator technology, devices and circuits (EUROSOI 2011) (Granada (Espagne), du 17/01/2011 au 19/01/2011). In: Proceedings of the Seventh Workshop of the Thematic Network on Silicon on Insulator technology, devices and circuits (EUROSOI 2011), 2011
Permanent URL http://hdl.handle.net/2078.1/87433