Standaert, François-Xavier
[UCL]
Rouvroy, Gaël
[UCL]
Quisquater, Jean-Jacques
[UCL]
Legat, Jean-Didier
[UCL]
The technical analysis used in determining which of the NESSIE candidates will
be selected as a standard block cipher includes efficiency testing of both hardware and software
implementations of candidate algorithms. Reprogrammable devices such as Field Programmable
Gate Arrays (FPGA’s) are highly attractive options for hardware implementations
of encryption algorithms and this report investigates the significance of FPGA implementations
of the block ciphers KHAZAD and MISTY1. A strong focus is placed on high throughput
circuits and we propose designs that unroll the cipher rounds and pipeline them in order to
optimize the frequency and throughput results. In addition, we implemented solutions that
allow to change the plaintext and the key on a cycle-by-cycle basis with no dead cycle. The
resulting designs fit on a VIRTEX1000 FPGA and have throughput between 8 and 9 Gbits/s.
This is an impressive result compared with existing FPGA implementations of block ciphers
within similar devices.
Bibliographic reference |
Standaert, François-Xavier ; Rouvroy, Gaël ; Quisquater, Jean-Jacques ; Legat, Jean-Didier. Efficient FPGA Implementations of Block Ciphers KHAZAD and MISTY1.Proceedings of the Third NESSIE Workshop (Munich, Germany, November 2002). |
Permanent URL |
http://hdl.handle.net/2078.1/81776 |