Measurement and two-dimensional simulation of thin-film SOI MOSFETs: Intrinsic gate capacitances at elevated temperatures

Intrinsic gate-capacitance characteristics of long-channel SOI MOSFETs are investigated by measurements up to 300 degrees C and by two-dimensional simulations up to 400 degrees C. Room temperature particularities related to impact ionization and floating body are successfully reproduced by a.c. simulations. Transient simulations are used in order to gain a deep physical insight into the observed phenomena. The contribution of majority carriers generated by impact ionization or back accumulation is clearly established. At high temperature, differences with room temperature behavior observed above and below threshold voltage are explained in terms of thermally generated excess carriers and impact ionization reduction. The analyzed features are the threshold voltage, the subthreshold slope, and particular humps near threshold and subthreshold capacitance values. Implications for analog or digital circuit operation are briefly discussed. Copyright (C) 1996 Elsevier Science Ltd