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Unified 1/f noise SOI MOSFET modelling for circuit simulation

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Iniguez, B. [Rensselaer Polytech. Inst., Troy, NY] Tambani, M Dessard, V. [UCL] Flandre, Denis [UCL]

The authors address the modelling of 1/f noise in SOI MOS devices for circuit simulation. A simple and unified model is presented which is valid for all operating regimes; it is verified by comparison with noise measurements. It is shown that this model is especially useful for low-power SOI MOS circuit design.

Document type Article de périodique (Journal article) – Article de recherche
Publication date 1997
Language Anglais
Journal information "Electronics Letters" - Vol. 33, no. 21, p. 1781-1782 (1997)
Peer reviewed yes
Publisher Iee-inst Elec Eng (Hertford)
issn 0013-5194
e-issn 1350-911X
Publication status Publié
Affiliation UCL - FSA/ELEC - Département d'électricité
Keywords MOS integrated circuits ; silicon-on-insulator ; circuit noise
Links
Bibliographic reference Iniguez, B. ; Tambani, M ; Dessard, V. ; Flandre, Denis. Unified 1/f noise SOI MOSFET modelling for circuit simulation. In: Electronics Letters, Vol. 33, no. 21, p. 1781-1782 (1997)
Permanent URL http://hdl.handle.net/2078.1/45483