Xu, Pengcheng
[UCL]
Gimeno Gasca, Cecilia
[UCL]
Bol, David
[UCL]
True Single Phase Clocked (TSPC) flip-flops (FF) are widely used in high-frequency dividers for their higher operation speed and lower power compared to Master-Slaver FFs. In this paper, we study the optimization of TSPC frequency dividers for always-on low-frequency clock division in ultra-low-power (ULP) SoCs. We analyze the architecture, operation principle and data loss problem in TSPC-based frequency divider. An optimization strategy based on selective gate length upsize is proposed to minimize power consumption by balancing switching and leakage power consumption. A 10-stage frequency divider was designed in 28 nm FDSOI CMOS and integrated in a ULP SoC. Post-layout simulations with 32-MHz input frequency show a power consumption of 28.3 nW with 0.8-V supply voltage.
Bibliographic reference |
Xu, Pengcheng ; Gimeno Gasca, Cecilia ; Bol, David. Optimizing TSPC Frequency Dividers for Always-On Low-Frequency Applications in 28nm FDSOI CMOS.2017 IEEE S3S Conference (San Francisco (USA), du 16/10/2017 au 19/10/2017). In: Proceedings of the 2017 IEEE S3S Conference, IEEE2017, p. 2 |
Permanent URL |
http://hdl.handle.net/2078.1/191118 |