Compensation of Total Ionizing Dose Effects in ULV SoCs Through Adaptive Voltage Scaling

De Vos, Julien [UCL] Kilchytska, Valeriya [UCL] Flandre, Denis [UCL] Bol, David [UCL]

Total ionizing dose (TID) jeopardizes the operation of ULV circuits by shifting the threshold voltage of the devices. Measurements on a 65nm SoC show that it modifies the output of an on-chip 4-T voltage reference by 3.5% and the gate delay at ULV by 17%. This harms the timing closure of ULV digital systems based a conventional power management architecture generating constant clock frequency and supply voltage. We show by experimental measurements that the use of an on-chip adaptive voltage scaling system efficiently cancels these effects of TID for robust timing closure at ULV.