User menu

Accès à distance ? S'identifier sur le proxy UCLouvain

Improved synthesis of gain-boosted regulated-cascode CMOS stages using symbolic analysis and gm/ID methodology

Primary tabs

Flandre, Denis [UCL] Viviani, A. [UCL] Eggermont, Jean-Pierre [UCL] Gentinne, B. [UCL] Jespers, Paul [UCL]

A systematic study of the gain-boosted regulated-cascode operational transconductance amplifier (OTA) CMOS stage is presented. Symbolic analysis is used first to describe the pole-zero behaviour and second to propose design criteria for optimal settling time. A synthesis procedure based on the “gm/ID” methodology is considered further on for quick optimization of the architecture based on the dc open-loop gain, transition frequency, and settling time specifications. Practical design cases are finally discussed.

Document type Communication à un colloque (Conference Paper) – Présentation orale avec comité de sélection
Publication date 1997
Language Anglais
Conference "22nd European Solid-State Circuits Conference (ESSCIRC 1996)", Neuchatel (Suisse) (du 17/09/1996 au 19/09/1996)
Peer reviewed yes
Host document "Proceedings of the 22nd European Solid-State Circuits Conference (ESSCIRC 1996)"
Affiliation UCL - FSA/ELEC - Département d'électricité
Keywords CMOS analog integrated circuits ; Transient response ; Circuit stability ; Circuit synthesis ; Design optimization ; Frequency synthesizers ; Integrated circuit synthesis ; Operational amplifiers ; Optimization methods ; Transconductance
Links
Bibliographic reference Flandre, Denis ; Viviani, A. ; Eggermont, Jean-Pierre ; Gentinne, B. ; Jespers, Paul. Improved synthesis of gain-boosted regulated-cascode CMOS stages using symbolic analysis and gm/ID methodology.22nd European Solid-State Circuits Conference (ESSCIRC 1996) (Neuchatel (Suisse), du 17/09/1996 au 19/09/1996). In: Proceedings of the 22nd European Solid-State Circuits Conference (ESSCIRC 1996), 1997
Permanent URL http://hdl.handle.net/2078.1/134314