Pavanello, M.A.
[Centro Universitario da FEI, Brazil]
Cerdeira, A.
[SEES, CINVESTAV, Mexico]
Raskin, Jean-Pierre
[UCL]
Flandre, Denis
[UCL]
This work studies the linearity of conventional and Graded- Channel (GC) Gate-All-Around (GAA) devices when applied in 2- MOS and 4-MOS balanced structures operating as tunable resistors. The study has been performed through device characterization and two-dimensional process and device simulations. Total harmonic distortion (THD) and third order harmonic distortion (HD3) have been evaluated. When taking into account similar on-resistance, the use of the GC GAA transistors in both 2-MOS and 4-MOS structures improves the linearity. The use of GC GAA devices in 2-MOS balanced structures allows a reduction of the gate overdrive voltage of 22.5% without degrading THD and HD3. On the other hand, the use of GC GAA devices in 4-MOS structures leads to an improvement in both HD3 and THD by 7 dB for devices with similar channel length at the same gate voltage overdrive.
Bibliographic reference |
Pavanello, M.A. ; Cerdeira, A. ; Raskin, Jean-Pierre ; Flandre, Denis. Application of Double Gate Graded-Channel SOI in MOSFET-C Balanced Structures.211th Meeting of the Electrochemical Society – ECS’07 (Chicago, Illinois (USA), du 06/05/2007 au 11/05/2007). In: Proceedings of the 211th Meeting of the Electrochemical Society – ECS’07, 2007, p.Paper 734 |
Permanent URL |
http://hdl.handle.net/2078.1/123293 |