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Influence of gate underlap in AM and IM MuGFETs

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Lee, Chi-Woo [Tyndall National Institute, University of Cork] Afzalian, Aryan [UCL] Dehdashti, Nima [Tyndall National Institute, University of Cork] Xiong, Weize [Texas Instruments Inc., Dallas] Colinge, Jean-Pierre [Tyndall National Institute, University of Cork]

The influence of gate underlap on the electrical properties is analyzed. Both simulation results and experimental data show that in a device with gate underlap, accumulation-mode (AM) devices have a higher current drive, lower source and drain resistance and less process variability than inversion-mode (IM) FETs.

Document type Communication à un colloque (Conference Paper) – Présentation orale avec comité de sélection
Access type Accès restreint
Publication date 2008
Language Anglais
Conference "ESSDERC-ESSCIRC 2008", Edinburgh (UK) (du 15/09/2008 au 19/09/2008)
Peer reviewed yes
Host document "Proceedings of ESSDERC-ESSCIRC 2008"- p. 238-241 (ISBN : 978-1-4244-2363-7)
Publisher IEEE
Publication status Publié
Affiliation UCL - FSA/ELEC - Département d'électricité
Keywords MuFETs ; Accumulation-mode ; Inversion-mode ; AM ; IM
Links
Bibliographic reference Lee, Chi-Woo ; Afzalian, Aryan ; Dehdashti, Nima ; Xiong, Weize ; Colinge, Jean-Pierre. Influence of gate underlap in AM and IM MuGFETs.ESSDERC-ESSCIRC 2008 (Edinburgh (UK), du 15/09/2008 au 19/09/2008). In: Proceedings of ESSDERC-ESSCIRC 2008, IEEE2008, p. 238-241
Permanent URL http://hdl.handle.net/2078.1/120919