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Asymmetric Self-Cascode Configuration to Improve the Analog Performance of SOI nMOS Transistors

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De Souza, Michelly [Centro Universitário da FEI] Flandre, Denis [UCL] Pavanello, Marcelo Antonio [Centro Universitário da FEI]

A recent work showed that gD of long-channel self-cascode transistors can be further reduced by replacing M2 with a transistor with intrinsic concentration in the channel. In order to extend this proposal to more recent technologies, the current work presents an analysis of short-channel asymmetric self-cascode transistors implemented using a multi-threshold voltage commercial process. Numerical simulations were also performed aiming to extend the study, searching for the optimal doping concentration and length for M1 and M2.

Document type Communication à un colloque (Conference Paper) – Présentation orale avec comité de sélection
Publication date 2011
Language Anglais
Conference "IEEE International SOI Conference (SOI 2011)", Tempe (USA) (du 03/10/2011 au 06/10/2011)
Peer reviewed yes
Host document "Proceedings of the IEEE International SOI Conference (SOI 2011)"- 1-2 (ISBN : 978-1-61284-761-0)
Affiliations Centro Universitário da FEI - Department of Electrical Engineering
UCL - SST/ICTM/ELEN - Pôle en ingénierie électrique
Keywords Degradation ; Doping ; Logic gates ; MOSFETs ; Numerical simulation ; Threshold voltage
Links
Bibliographic reference De Souza, Michelly ; Flandre, Denis ; Pavanello, Marcelo Antonio. Asymmetric Self-Cascode Configuration to Improve the Analog Performance of SOI nMOS Transistors.IEEE International SOI Conference (SOI 2011) (Tempe (USA), du 03/10/2011 au 06/10/2011). In: Proceedings of the IEEE International SOI Conference (SOI 2011), 2011, p.1-2
Permanent URL http://hdl.handle.net/2078.1/106361