Architecture and high-level synthesis of tag-tree coding for a potential A-DSC video compression standard

The constant quality increase of video contents brings important constraints on the infrastructures and links involved in the storage and transport of video signals. An approach gaining more and more attention is to reduce the bandwidth of video streams by means of light compression. In this context, new real-time, visually lossless compression algorithms have arose, targeting fixed compression rates that allow the transport of high-quality video streams on existing infrastructures. Among these algorithms, the VESA consortium standardized the Display Stream Compression (dsc) codec. VESA is now willing to complement DSC by an advanced version (a-dsc), achieving a higher compression rate at the expense of an increased complexity. A full answer to VESA’s a-dsc call-for-technology has been proposed. It has the form of a multi-mode codec. In the same context, Intopix developed a codec named Tico. The particularly low complexity of Tico is such that it can be envisioned as being one compression mode inside a-dsc. A first integration proposal of Tico in a-dsc has been realized. To achieve good performances, the minimalist Tico embedded inside a-dsc requires an experimental encoding method: tag-tree coding, which is modelled in software but has not been implemented in hardware yet. This master thesis studies the hardware implementation of tag-tree coding in field programmable gate array (FPGA) devices for an integration inside Tico. The attention is put on the encoder, targeting the processing of 4 pixels per clock cycle. Different hardware architectures based on a common template are proposed, aiming at achieving minimal hardware complexity. High-level synthesis is used to partly implement this architecture in an Altera Stratix V device operated at 300 MHz. An image distortion measurement campaign is carried out with the Tico reference software, allowing to put the hardware requirements of tag-tree coding in perspective with the image quality improvements it brings. Other use cases than the integration inside a-dsc are investigated for tag-tree coding. This work aims at discussing different architectural possibilities for the encoder part of tag-tree coding, as well as its integration inside Tico. It provides an interesting basis for a complete, efficient hardware implementation of tag-tree coding.