Porting of the TICO video compression algorithm from FPGA to custom IC implementations through HLS

The video compression sector evolves at a fast rhythm and the dedicated hardware tools have to follow at the same pace. IntoPIX, a reference provider of JPEG-2000 compression tools, developped for the industry the TICO, a lossless and light-weight compression technology. The design was synthesized through High Level Synthesis for FPGAs. To target a wider market, the algorithm has also to be implemented as a dedicated processor in an ASIC technology. The goal of the thesis is the porting of the TICO algorithm from an FPGA to a custom IC implementation. The algorithm written in C++ was provided by IntoPIX which uses the High Level Synthesis to create the hardware design. First of all, the modifications of the software constraints needed to comply with the new hardware constraints are discussed. The initiation interval is bound to the hardware and has to be choosen subsequently. The results also highlight a mismatch in the timing of the libraries used at the different stages of the design flow. Then, the choices in term of memory types are investigated and the hardware and software handling of the memory are compared. The RTL code for the hardware memory handling is exposed as it represent significant savings in term of area. Afterwards, the influence of different algorithm parameters is analyzed to have a deeper understanding of the resulting design performances. Finally, the entire TICO algorithm is synthesized in the 65nm CMOS technology at 400MHZ and for specific parameters with a resulting total area of 3 250 000μm2 which represents 431kGates and 2224kbits of memory.