Study and performance analysis of cache coherence protocols in shared-memory multiprocessors

Cache coherence is one of the main challenges to tackle when designing a shared-memory multiprocessors system. Incoherence may happen when multiple actors in a system are working on the same pieces of data without any coordination. This coordination is brought by the coherence protocol : a set of finite states machines, managing the caches and memory and keeping the coherence invariants true. This master’s thesis aims at introducing cache coherence in details and providing a high-level performance analysis of some state-of-the art protocols. First, shared-memory multiprocessors are briefly introduced. Then, a substantial bibliographical summary of cache coherence protocol design is proposed. Afterwards, gem5, an architectural simulator, and the way coherence protocols are designed into it are introduced. A simulation framework adapted to the problematic is then designed to run on the simulator. Eventually, several coherence protocols and their associated memory hierarchies are simulated and analysed to highlight the performance impact of finer-designed protocols and their reaction faced to qualitative and quantitative changes into the hierarchy.