Fault and side-channel resistant devices using non-linear robust codes and higher-order masking

This master thesis aims at securing cryptographic devices against two common types of attacks: side-channel attacks and fault attacks, using algorithmic methods. This work presents some state-of-art techniques to protect AES implementations against these attacks separately, studies the performance of selected schemes and exposes a weakness in modern algorithmic fault countermeasures used for SP networks. Furthermore, it proposes two ways to protect against those attacks simultaneously and confirms that the costs of these solutions do not introduce higher complexity with respect to the order of protection. For all the implementations, costs were evaluated in terms of execution time and memory costs and the combined solutions were compared to modern masked implementations of the AES. The last part of this work presents a laser attack setup made from scratch and shows how to sucessfully insert faults on a AVR Atmel ATMega644P chip, even when it is protected from faults with the suggested method, as there is a security hole. New countermeasures for faults are also suggested to protect from this breach.