Assessment of the split CV mobility extraction method in 28nm FDSOI transistors

Extraction of the effective carrier mobility is of major importance to evaluate the transport characteristics and performances of advanced transistors. The relative importance of parasitics has however increased with reduction of the gate length. Mobility extraction methods initially designed for long devices must therefore be adapted by including proper correction for these parasitcs in highly scaled nodes. In this work, the application of the well known split CV method is assessed in 28FDSOI transistors with gate length down to 25 nm using TCAD simulations. The conventional split CV method is shown unable to extract the mobility correctly in short FDSOI transistors. This limitation is attributed to the increased impact of underlap-related parasitics neglected by the method’s implicit assumptions. The significant bias dependence of the access resistance and the non-negligible contribution of the inner finging capacitance are notably identified as the main sources of mobility underestimation by the split CV method in these short FDSOI transistors. An improved split CV extraction procedure accounting for these parasitics is then shown able to extract the effective mobility in strong inversion within less than 10% variation from the TCAD implemented model for gate lengths down to 25 nm. Measurements on 28FDSOI transistors are seen to qualitatively confirm the insights from the TCAD simulations.