Usage of multi-bit flip-flops in ultra-low-power MCUs and DSPs

Nowadays, one of the main drives in digital design research is power reduction. Indeed, with the rise of the Internet of things and embedded devices, the demand for low-voltage and ultra-low power devices is at an all-time high and will continue to rise in the coming years. This quest for power reduction is enabled by technical and architectural advances. Technical breakthroughs in fabrication have been made, with the emergence of new devices (FDSOI, FinFet) as well as the ever diminishing channel lengths. At the same time, architectural improvements were made with techniques such as power gating, clock gating and dark silicon. This work’s main focus is to reduce the power consumption of the clock and sequential elements of a design. We will look at one of the most recent architectural solution that tries to improve the single-bit flip-flop, the main building blocks of sequential circuits. This architectural solution is the multi-bit flip-flop. We will characterise those cells and then implement them in a commercially available design to evaluate the possible benefits of the technology.