High quality substrate for high frequency FD SOI technology

High-resistivity (HR) silicon-on-insulator substrates for RFICs have been widely investigated and developed as promising candidates for integration with FD SOI digital technology. The key issue is increasing their high effective resistivity, which suffers from the parasitic surface conductance (PSC) effect. In a recent work, an fully CMOS-compatible alternative to the commercially available trap-rich substrate was presented. By introducing a series of P-N junctions below the oxide, high resistivity depletion regions are created, and the PSC effect is reduced. In this thesis, experimental results on CPW lines prove that intermediate performance is achieved between trap-rich and HR-Si. TCAD simulations using Silvaco Atlas then show that further performance increase is possible in terms of effective resistivity and harmonic distortion, by increasing the density of P-N junctions with high-resolution lithography or by reverse biasing them to increase the depletion width. Finally, high-temperature small- and large-signal measurements show good performance up to 100°C.